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1b1247dd75
Ricoh power management IC RC5T583 contains is multi functional device having multiple sub devices inside this. This device has multiple dcdc/ldo regulators, gpios, interrupt controllers, on-key, RTCs, ADCs. This device have 4 DCDCs, 8 LDOs, 8 GPIOs, 6 ADCs, 3 RTCs etc. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
409 lines
12 KiB
C
409 lines
12 KiB
C
/*
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* Interrupt driver for RICOH583 power management chip.
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*
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* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
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* Author: Laxman dewangan <ldewangan@nvidia.com>
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*
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* based on code
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* Copyright (C) 2011 RICOH COMPANY,LTD
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/mfd/rc5t583.h>
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enum int_type {
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SYS_INT = 0x1,
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DCDC_INT = 0x2,
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RTC_INT = 0x4,
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ADC_INT = 0x8,
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GPIO_INT = 0x10,
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};
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static int gpedge_add[] = {
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RC5T583_GPIO_GPEDGE2,
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RC5T583_GPIO_GPEDGE2
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};
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static int irq_en_add[] = {
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RC5T583_INT_EN_SYS1,
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RC5T583_INT_EN_SYS2,
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RC5T583_INT_EN_DCDC,
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RC5T583_INT_EN_RTC,
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RC5T583_INT_EN_ADC1,
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RC5T583_INT_EN_ADC2,
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RC5T583_INT_EN_ADC3,
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RC5T583_GPIO_EN_INT
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};
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static int irq_mon_add[] = {
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RC5T583_INT_MON_SYS1,
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RC5T583_INT_MON_SYS2,
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RC5T583_INT_MON_DCDC,
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RC5T583_INT_MON_RTC,
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RC5T583_INT_IR_ADCL,
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RC5T583_INT_IR_ADCH,
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RC5T583_INT_IR_ADCEND,
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RC5T583_INT_IR_GPIOF,
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RC5T583_INT_IR_GPIOR
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};
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static int irq_clr_add[] = {
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RC5T583_INT_IR_SYS1,
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RC5T583_INT_IR_SYS2,
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RC5T583_INT_IR_DCDC,
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RC5T583_INT_IR_RTC,
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RC5T583_INT_IR_ADCL,
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RC5T583_INT_IR_ADCH,
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RC5T583_INT_IR_ADCEND,
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RC5T583_INT_IR_GPIOF,
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RC5T583_INT_IR_GPIOR
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};
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static int main_int_type[] = {
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SYS_INT,
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SYS_INT,
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DCDC_INT,
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RTC_INT,
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ADC_INT,
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ADC_INT,
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ADC_INT,
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GPIO_INT,
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GPIO_INT,
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};
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struct rc5t583_irq_data {
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u8 int_type;
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u8 master_bit;
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u8 int_en_bit;
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u8 mask_reg_index;
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int grp_index;
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};
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#define RC5T583_IRQ(_int_type, _master_bit, _grp_index, \
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_int_bit, _mask_ind) \
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{ \
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.int_type = _int_type, \
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.master_bit = _master_bit, \
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.grp_index = _grp_index, \
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.int_en_bit = _int_bit, \
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.mask_reg_index = _mask_ind, \
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}
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static const struct rc5t583_irq_data rc5t583_irqs[RC5T583_MAX_IRQS] = {
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[RC5T583_IRQ_ONKEY] = RC5T583_IRQ(SYS_INT, 0, 0, 0, 0),
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[RC5T583_IRQ_ACOK] = RC5T583_IRQ(SYS_INT, 0, 1, 1, 0),
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[RC5T583_IRQ_LIDOPEN] = RC5T583_IRQ(SYS_INT, 0, 2, 2, 0),
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[RC5T583_IRQ_PREOT] = RC5T583_IRQ(SYS_INT, 0, 3, 3, 0),
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[RC5T583_IRQ_CLKSTP] = RC5T583_IRQ(SYS_INT, 0, 4, 4, 0),
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[RC5T583_IRQ_ONKEY_OFF] = RC5T583_IRQ(SYS_INT, 0, 5, 5, 0),
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[RC5T583_IRQ_WD] = RC5T583_IRQ(SYS_INT, 0, 7, 7, 0),
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[RC5T583_IRQ_EN_PWRREQ1] = RC5T583_IRQ(SYS_INT, 0, 8, 0, 1),
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[RC5T583_IRQ_EN_PWRREQ2] = RC5T583_IRQ(SYS_INT, 0, 9, 1, 1),
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[RC5T583_IRQ_PRE_VINDET] = RC5T583_IRQ(SYS_INT, 0, 10, 2, 1),
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[RC5T583_IRQ_DC0LIM] = RC5T583_IRQ(DCDC_INT, 1, 0, 0, 2),
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[RC5T583_IRQ_DC1LIM] = RC5T583_IRQ(DCDC_INT, 1, 1, 1, 2),
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[RC5T583_IRQ_DC2LIM] = RC5T583_IRQ(DCDC_INT, 1, 2, 2, 2),
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[RC5T583_IRQ_DC3LIM] = RC5T583_IRQ(DCDC_INT, 1, 3, 3, 2),
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[RC5T583_IRQ_CTC] = RC5T583_IRQ(RTC_INT, 2, 0, 0, 3),
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[RC5T583_IRQ_YALE] = RC5T583_IRQ(RTC_INT, 2, 5, 5, 3),
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[RC5T583_IRQ_DALE] = RC5T583_IRQ(RTC_INT, 2, 6, 6, 3),
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[RC5T583_IRQ_WALE] = RC5T583_IRQ(RTC_INT, 2, 7, 7, 3),
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[RC5T583_IRQ_AIN1L] = RC5T583_IRQ(ADC_INT, 3, 0, 0, 4),
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[RC5T583_IRQ_AIN2L] = RC5T583_IRQ(ADC_INT, 3, 1, 1, 4),
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[RC5T583_IRQ_AIN3L] = RC5T583_IRQ(ADC_INT, 3, 2, 2, 4),
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[RC5T583_IRQ_VBATL] = RC5T583_IRQ(ADC_INT, 3, 3, 3, 4),
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[RC5T583_IRQ_VIN3L] = RC5T583_IRQ(ADC_INT, 3, 4, 4, 4),
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[RC5T583_IRQ_VIN8L] = RC5T583_IRQ(ADC_INT, 3, 5, 5, 4),
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[RC5T583_IRQ_AIN1H] = RC5T583_IRQ(ADC_INT, 3, 6, 0, 5),
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[RC5T583_IRQ_AIN2H] = RC5T583_IRQ(ADC_INT, 3, 7, 1, 5),
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[RC5T583_IRQ_AIN3H] = RC5T583_IRQ(ADC_INT, 3, 8, 2, 5),
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[RC5T583_IRQ_VBATH] = RC5T583_IRQ(ADC_INT, 3, 9, 3, 5),
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[RC5T583_IRQ_VIN3H] = RC5T583_IRQ(ADC_INT, 3, 10, 4, 5),
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[RC5T583_IRQ_VIN8H] = RC5T583_IRQ(ADC_INT, 3, 11, 5, 5),
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[RC5T583_IRQ_ADCEND] = RC5T583_IRQ(ADC_INT, 3, 12, 0, 6),
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[RC5T583_IRQ_GPIO0] = RC5T583_IRQ(GPIO_INT, 4, 0, 0, 7),
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[RC5T583_IRQ_GPIO1] = RC5T583_IRQ(GPIO_INT, 4, 1, 1, 7),
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[RC5T583_IRQ_GPIO2] = RC5T583_IRQ(GPIO_INT, 4, 2, 2, 7),
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[RC5T583_IRQ_GPIO3] = RC5T583_IRQ(GPIO_INT, 4, 3, 3, 7),
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[RC5T583_IRQ_GPIO4] = RC5T583_IRQ(GPIO_INT, 4, 4, 4, 7),
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[RC5T583_IRQ_GPIO5] = RC5T583_IRQ(GPIO_INT, 4, 5, 5, 7),
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[RC5T583_IRQ_GPIO6] = RC5T583_IRQ(GPIO_INT, 4, 6, 6, 7),
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[RC5T583_IRQ_GPIO7] = RC5T583_IRQ(GPIO_INT, 4, 7, 7, 7),
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};
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static void rc5t583_irq_lock(struct irq_data *irq_data)
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{
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struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
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mutex_lock(&rc5t583->irq_lock);
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}
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static void rc5t583_irq_unmask(struct irq_data *irq_data)
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{
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struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
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unsigned int __irq = irq_data->irq - rc5t583->irq_base;
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const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
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rc5t583->group_irq_en[data->grp_index] |= 1 << data->grp_index;
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rc5t583->intc_inten_reg |= 1 << data->master_bit;
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rc5t583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit;
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}
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static void rc5t583_irq_mask(struct irq_data *irq_data)
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{
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struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
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unsigned int __irq = irq_data->irq - rc5t583->irq_base;
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const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
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rc5t583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index);
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if (!rc5t583->group_irq_en[data->grp_index])
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rc5t583->intc_inten_reg &= ~(1 << data->master_bit);
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rc5t583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit);
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}
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static int rc5t583_irq_set_type(struct irq_data *irq_data, unsigned int type)
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{
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struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
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unsigned int __irq = irq_data->irq - rc5t583->irq_base;
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const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
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int val = 0;
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int gpedge_index;
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int gpedge_bit_pos;
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/* Supporting only trigger level inetrrupt */
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if ((data->int_type & GPIO_INT) && (type & IRQ_TYPE_EDGE_BOTH)) {
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gpedge_index = data->int_en_bit / 4;
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gpedge_bit_pos = data->int_en_bit % 4;
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if (type & IRQ_TYPE_EDGE_FALLING)
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val |= 0x2;
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if (type & IRQ_TYPE_EDGE_RISING)
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val |= 0x1;
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rc5t583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
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rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
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rc5t583_irq_unmask(irq_data);
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return 0;
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}
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return -EINVAL;
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}
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static void rc5t583_irq_sync_unlock(struct irq_data *irq_data)
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{
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struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
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int i;
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int ret;
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for (i = 0; i < ARRAY_SIZE(rc5t583->gpedge_reg); i++) {
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ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
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rc5t583->gpedge_reg[i]);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in writing reg 0x%02x error: %d\n",
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gpedge_add[i], ret);
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}
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for (i = 0; i < ARRAY_SIZE(rc5t583->irq_en_reg); i++) {
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ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
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rc5t583->irq_en_reg[i]);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in writing reg 0x%02x error: %d\n",
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irq_en_add[i], ret);
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}
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ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN,
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rc5t583->intc_inten_reg);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in writing reg 0x%02x error: %d\n",
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RC5T583_INTC_INTEN, ret);
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mutex_unlock(&rc5t583->irq_lock);
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}
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#ifdef CONFIG_PM_SLEEP
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static int rc5t583_irq_set_wake(struct irq_data *irq_data, unsigned int on)
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{
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struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
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return irq_set_irq_wake(rc5t583->chip_irq, on);
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}
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#else
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#define rc5t583_irq_set_wake NULL
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#endif
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static irqreturn_t rc5t583_irq(int irq, void *data)
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{
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struct rc5t583 *rc5t583 = data;
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uint8_t int_sts[RC5T583_MAX_INTERRUPT_MASK_REGS];
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uint8_t master_int;
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int i;
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int ret;
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unsigned int rtc_int_sts = 0;
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/* Clear the status */
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for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++)
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int_sts[i] = 0;
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ret = rc5t583_read(rc5t583->dev, RC5T583_INTC_INTMON, &master_int);
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if (ret < 0) {
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dev_err(rc5t583->dev,
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"Error in reading reg 0x%02x error: %d\n",
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RC5T583_INTC_INTMON, ret);
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return IRQ_HANDLED;
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}
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for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; ++i) {
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if (!(master_int & main_int_type[i]))
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continue;
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ret = rc5t583_read(rc5t583->dev, irq_mon_add[i], &int_sts[i]);
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if (ret < 0) {
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dev_warn(rc5t583->dev,
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"Error in reading reg 0x%02x error: %d\n",
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irq_mon_add[i], ret);
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int_sts[i] = 0;
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continue;
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}
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if (main_int_type[i] & RTC_INT) {
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rtc_int_sts = 0;
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if (int_sts[i] & 0x1)
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rtc_int_sts |= BIT(6);
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if (int_sts[i] & 0x2)
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rtc_int_sts |= BIT(7);
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if (int_sts[i] & 0x4)
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rtc_int_sts |= BIT(0);
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if (int_sts[i] & 0x8)
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rtc_int_sts |= BIT(5);
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}
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ret = rc5t583_write(rc5t583->dev, irq_clr_add[i],
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~int_sts[i]);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in reading reg 0x%02x error: %d\n",
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irq_clr_add[i], ret);
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if (main_int_type[i] & RTC_INT)
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int_sts[i] = rtc_int_sts;
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}
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/* Merge gpio interrupts for rising and falling case*/
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int_sts[7] |= int_sts[8];
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/* Call interrupt handler if enabled */
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for (i = 0; i < RC5T583_MAX_IRQS; ++i) {
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const struct rc5t583_irq_data *data = &rc5t583_irqs[i];
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if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&
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(rc5t583->group_irq_en[data->master_bit] &
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(1 << data->grp_index)))
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handle_nested_irq(rc5t583->irq_base + i);
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}
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return IRQ_HANDLED;
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}
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static struct irq_chip rc5t583_irq_chip = {
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.name = "rc5t583-irq",
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.irq_mask = rc5t583_irq_mask,
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.irq_unmask = rc5t583_irq_unmask,
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.irq_bus_lock = rc5t583_irq_lock,
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.irq_bus_sync_unlock = rc5t583_irq_sync_unlock,
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.irq_set_type = rc5t583_irq_set_type,
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.irq_set_wake = rc5t583_irq_set_wake,
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};
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int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base)
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{
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int i, ret;
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if (!irq_base) {
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dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");
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return -EINVAL;
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}
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mutex_init(&rc5t583->irq_lock);
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/* Initailize all int register to 0 */
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for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) {
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ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
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rc5t583->irq_en_reg[i]);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in writing reg 0x%02x error: %d\n",
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irq_en_add[i], ret);
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}
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for (i = 0; i < RC5T583_MAX_GPEDGE_REG; i++) {
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ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
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rc5t583->gpedge_reg[i]);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in writing reg 0x%02x error: %d\n",
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gpedge_add[i], ret);
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}
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ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 0x0);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in writing reg 0x%02x error: %d\n",
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RC5T583_INTC_INTEN, ret);
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/* Clear all interrupts in case they woke up active. */
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for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) {
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ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 0);
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if (ret < 0)
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dev_warn(rc5t583->dev,
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"Error in writing reg 0x%02x error: %d\n",
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irq_clr_add[i], ret);
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}
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rc5t583->irq_base = irq_base;
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rc5t583->chip_irq = irq;
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for (i = 0; i < RC5T583_MAX_IRQS; i++) {
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|
int __irq = i + rc5t583->irq_base;
|
|
irq_set_chip_data(__irq, rc5t583);
|
|
irq_set_chip_and_handler(__irq, &rc5t583_irq_chip,
|
|
handle_simple_irq);
|
|
irq_set_nested_thread(__irq, 1);
|
|
#ifdef CONFIG_ARM
|
|
set_irq_flags(__irq, IRQF_VALID);
|
|
#endif
|
|
}
|
|
|
|
ret = request_threaded_irq(irq, NULL, rc5t583_irq, IRQF_ONESHOT,
|
|
"rc5t583", rc5t583);
|
|
if (ret < 0)
|
|
dev_err(rc5t583->dev,
|
|
"Error in registering interrupt error: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
int rc5t583_irq_exit(struct rc5t583 *rc5t583)
|
|
{
|
|
if (rc5t583->chip_irq)
|
|
free_irq(rc5t583->chip_irq, rc5t583);
|
|
return 0;
|
|
}
|