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e0018afec5
This adds support for "output to Trace Transport subsystem" capability of Intel PT. It means that PT can output its trace to an MMIO address range rather than system memory buffer. Acked-by: Song Liu <songliubraving@fb.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_INTEL_PT_H
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#define _ASM_X86_INTEL_PT_H
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#define PT_CPUID_LEAVES 2
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#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
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enum pt_capabilities {
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PT_CAP_max_subleaf = 0,
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PT_CAP_cr3_filtering,
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PT_CAP_psb_cyc,
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PT_CAP_ip_filtering,
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PT_CAP_mtc,
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PT_CAP_ptwrite,
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PT_CAP_power_event_trace,
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PT_CAP_topa_output,
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PT_CAP_topa_multiple_entries,
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PT_CAP_single_range_output,
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PT_CAP_output_subsys,
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PT_CAP_payloads_lip,
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PT_CAP_num_address_ranges,
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PT_CAP_mtc_periods,
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PT_CAP_cycle_thresholds,
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PT_CAP_psb_periods,
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};
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
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void cpu_emergency_stop_pt(void);
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extern u32 intel_pt_validate_hw_cap(enum pt_capabilities cap);
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extern u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities cap);
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#else
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static inline void cpu_emergency_stop_pt(void) {}
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static inline u32 intel_pt_validate_hw_cap(enum pt_capabilities cap) { return 0; }
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static inline u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability) { return 0; }
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#endif
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#endif /* _ASM_X86_INTEL_PT_H */
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