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23f5cace4f
CNS3xxx chips have AHCI-compatible SATA controller. This patch adds the support using generic ahci_platform driver. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
153 lines
3.5 KiB
C
153 lines
3.5 KiB
C
/*
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* Cavium Networks CNS3420 Validation Board
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*
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* Copyright 2000 Deep Blue Solutions Ltd
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* Copyright 2008 ARM Limited
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* Copyright 2008 Cavium Networks
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* Scott Shu
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* Copyright 2010 MontaVista Software, LLC.
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* Anton Vorontsov <avorontsov@mvista.com>
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/io.h>
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/partitions.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/hardware.h>
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#include <mach/cns3xxx.h>
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#include <mach/irqs.h>
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#include "core.h"
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#include "devices.h"
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/*
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* NOR Flash
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*/
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static struct mtd_partition cns3420_nor_partitions[] = {
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{
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.name = "uboot",
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.size = 0x00040000,
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.offset = 0,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.size = 0x004C0000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "filesystem",
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.size = 0x7000000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "filesystem2",
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.size = 0x0AE0000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "ubootenv",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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},
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};
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static struct physmap_flash_data cns3420_nor_pdata = {
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.width = 2,
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.parts = cns3420_nor_partitions,
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.nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
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};
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static struct resource cns3420_nor_res = {
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.start = CNS3XXX_FLASH_BASE,
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.end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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};
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static struct platform_device cns3420_nor_pdev = {
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.name = "physmap-flash",
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.id = 0,
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.resource = &cns3420_nor_res,
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.num_resources = 1,
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.dev = {
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.platform_data = &cns3420_nor_pdata,
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},
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};
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/*
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* UART
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*/
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static void __init cns3420_early_serial_setup(void)
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{
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#ifdef CONFIG_SERIAL_8250_CONSOLE
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static struct uart_port cns3420_serial_port = {
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.membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
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.mapbase = CNS3XXX_UART0_BASE,
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.irq = IRQ_CNS3XXX_UART0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
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.regshift = 2,
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.uartclk = 24000000,
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.line = 0,
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.type = PORT_16550A,
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.fifosize = 16,
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};
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early_serial_setup(&cns3420_serial_port);
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#endif
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}
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/*
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* Initialization
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*/
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static struct platform_device *cns3420_pdevs[] __initdata = {
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&cns3420_nor_pdev,
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};
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static void __init cns3420_init(void)
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{
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platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
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cns3xxx_ahci_init();
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cns3xxx_sdhci_init();
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pm_power_off = cns3xxx_power_off;
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}
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static struct map_desc cns3420_io_desc[] __initdata = {
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{
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.virtual = CNS3XXX_UART0_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static void __init cns3420_map_io(void)
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{
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cns3xxx_map_io();
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iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
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cns3420_early_serial_setup();
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}
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MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
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.phys_io = CNS3XXX_UART0_BASE,
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.io_pg_offst = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.map_io = cns3420_map_io,
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.init_irq = cns3xxx_init_irq,
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.timer = &cns3xxx_timer,
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.init_machine = cns3420_init,
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MACHINE_END
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