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20434dc92c
The i.MX 7ULP family of processors features NXP's advanced implementation of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). This patch aims to add the initial support including: 1) CLK 2) GPIO PTC, PTD, PTE, PTF 3) uSDHC 1/2 4) LPUART 4/5/6/7 5) LPI2C 6/7 Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
347 lines
9.3 KiB
Plaintext
347 lines
9.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx7ulp-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "imx7ulp-pinfunc.h"
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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gpio0 = &gpio_ptc;
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gpio1 = &gpio_ptd;
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gpio2 = &gpio_pte;
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gpio3 = &gpio_ptf;
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i2c0 = &lpi2c6;
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i2c1 = &lpi2c7;
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mmc0 = &usdhc0;
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mmc1 = &usdhc1;
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serial0 = &lpuart4;
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serial1 = &lpuart5;
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serial2 = &lpuart6;
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serial3 = &lpuart7;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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};
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intc: interrupt-controller@40021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x40021000 0x1000>,
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<0x40022000 0x1000>;
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};
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rosc: clock-rosc {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "rosc";
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#clock-cells = <0>;
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};
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sosc: clock-sosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "sosc";
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#clock-cells = <0>;
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};
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sirc: clock-sirc {
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-output-names = "sirc";
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#clock-cells = <0>;
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};
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firc: clock-firc {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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clock-output-names = "firc";
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#clock-cells = <0>;
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};
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upll: clock-upll {
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compatible = "fixed-clock";
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clock-frequency = <480000000>;
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clock-output-names = "upll";
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#clock-cells = <0>;
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};
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mpll: clock-mpll {
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compatible = "fixed-clock";
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clock-frequency = <480000000>;
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clock-output-names = "mpll";
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#clock-cells = <0>;
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};
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ahbbridge0: bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40000000 0x800000>;
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ranges;
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lpuart4: serial@402d0000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x402d0000 0x1000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
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clock-names = "ipg";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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assigned-clock-rates = <24000000>;
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status = "disabled";
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};
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lpuart5: serial@402e0000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x402e0000 0x1000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
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clock-names = "ipg";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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tpm5: tpm@40260000 {
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compatible = "fsl,imx7ulp-tpm";
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reg = <0x40260000 0x1000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&pcc2 IMX7ULP_CLK_LPTPM5>;
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clock-names = "ipg", "per";
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};
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usdhc0: mmc@40370000 {
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compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
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reg = <0x40370000 0x10000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC0>;
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clock-names ="ipg", "ahb", "per";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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usdhc1: mmc@40380000 {
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compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
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reg = <0x40380000 0x10000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC1>;
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clock-names ="ipg", "ahb", "per";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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scg1: clock-controller@403e0000 {
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compatible = "fsl,imx7ulp-scg1";
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reg = <0x403e0000 0x10000>;
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clocks = <&rosc>, <&sosc>, <&sirc>,
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<&firc>, <&upll>, <&mpll>;
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clock-names = "rosc", "sosc", "sirc",
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"firc", "upll", "mpll";
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#clock-cells = <1>;
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};
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pcc2: clock-controller@403f0000 {
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compatible = "fsl,imx7ulp-pcc2";
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reg = <0x403f0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&scg1 IMX7ULP_CLK_DDR_DIV>,
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<&scg1 IMX7ULP_CLK_APLL_PFD2>,
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<&scg1 IMX7ULP_CLK_APLL_PFD1>,
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<&scg1 IMX7ULP_CLK_APLL_PFD0>,
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<&scg1 IMX7ULP_CLK_UPLL>,
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<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_MIPI_PLL>,
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<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_ROSC>,
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<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
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clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
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"apll_pfd2", "apll_pfd1", "apll_pfd0",
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"upll", "sosc_bus_clk", "mpll",
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"firc_bus_clk", "rosc", "spll_bus_clk";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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};
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smc1: smc1@40410000 {
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compatible = "fsl,imx7ulp-smc1";
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reg = <0x40410000 0x1000>;
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};
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pcc3: clock-controller@40b30000 {
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compatible = "fsl,imx7ulp-pcc3";
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reg = <0x40b30000 0x10000>;
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#clock-cells = <1>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&scg1 IMX7ULP_CLK_DDR_DIV>,
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<&scg1 IMX7ULP_CLK_APLL_PFD2>,
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<&scg1 IMX7ULP_CLK_APLL_PFD1>,
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<&scg1 IMX7ULP_CLK_APLL_PFD0>,
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<&scg1 IMX7ULP_CLK_UPLL>,
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<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_MIPI_PLL>,
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<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_ROSC>,
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<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
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clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
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"apll_pfd2", "apll_pfd1", "apll_pfd0",
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"upll", "sosc_bus_clk", "mpll",
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"firc_bus_clk", "rosc", "spll_bus_clk";
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};
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};
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ahbbridge1: bus@40800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40800000 0x800000>;
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ranges;
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lpi2c6: i2c@40a40000 {
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compatible = "fsl,imx7ulp-lpi2c";
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reg = <0x40a40000 0x10000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
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clock-names = "ipg";
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assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpi2c7: i2c@40a50000 {
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compatible = "fsl,imx7ulp-lpi2c";
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reg = <0x40a50000 0x10000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
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clock-names = "ipg";
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assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpuart6: serial@40a60000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x40a60000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
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clock-names = "ipg";
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assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpuart7: serial@40a70000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x40a70000 0x1000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
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clock-names = "ipg";
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assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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iomuxc1: pinctrl@40ac0000 {
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compatible = "fsl,imx7ulp-iomuxc1";
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reg = <0x40ac0000 0x1000>;
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};
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gpio_ptc: gpio@40ae0000 {
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compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
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reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
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<&pcc3 IMX7ULP_CLK_PCTLC>;
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clock-names = "gpio", "port";
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gpio-ranges = <&iomuxc1 0 0 32>;
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};
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gpio_ptd: gpio@40af0000 {
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compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
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reg = <0x40af0000 0x1000 0x400f0040 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
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<&pcc3 IMX7ULP_CLK_PCTLD>;
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clock-names = "gpio", "port";
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gpio-ranges = <&iomuxc1 0 32 32>;
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};
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gpio_pte: gpio@40b00000 {
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compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
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reg = <0x40b00000 0x1000 0x400f0080 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
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<&pcc3 IMX7ULP_CLK_PCTLE>;
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clock-names = "gpio", "port";
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gpio-ranges = <&iomuxc1 0 64 32>;
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};
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gpio_ptf: gpio@40b10000 {
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compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
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reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
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<&pcc3 IMX7ULP_CLK_PCTLF>;
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clock-names = "gpio", "port";
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gpio-ranges = <&iomuxc1 0 96 32>;
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};
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};
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};
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