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The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
73 lines
2.9 KiB
Plaintext
73 lines
2.9 KiB
Plaintext
Device Tree Clock bindings for arch-sunxi
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"allwinner,sun4i-osc-clk" - for a gatable oscillator
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"allwinner,sun4i-pll1-clk" - for the main PLL clock
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-axi-clk" - for the AXI clock
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"allwinner,sun4i-axi-gates-clk" - for the AXI gates
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"allwinner,sun4i-ahb-clk" - for the AHB clock
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"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
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"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
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"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
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"allwinner,sun4i-apb0-clk" - for the APB0 clock
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"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
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"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
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"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
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"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
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"allwinner,sun4i-apb1-clk" - for the APB1 clock
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"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
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"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
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"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
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"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
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"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
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"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
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"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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- clocks : shall be the input parent clock(s) phandle for the clock
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- #clock-cells : from common clock binding; shall be set to 0 except for
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"allwinner,*-gates-clk" where it shall be set to 1
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Additionally, "allwinner,*-gates-clk" clocks require:
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- clock-output-names : the corresponding gate names that the clock controls
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Clock consumers should specify the desired clocks they use with a
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"clocks" phandle cell. Consumers that are using a gated clock should
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provide an additional ID in their clock property. The values of this
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ID are documented in sunxi/<soc>-gates.txt.
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For example:
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M_fixed>;
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};
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pll1: pll1@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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};
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>;
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};
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