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1f911c3a11
* for-next/52-bit-pa: arm64: enable 52-bit physical address support arm64: allow ID map to be extended to 52 bits arm64: handle 52-bit physical addresses in page table entries arm64: don't open code page table entry creation arm64: head.S: handle 52-bit PAs in PTEs in early page table setup arm64: handle 52-bit addresses in TTBR arm64: limit PA size to supported range arm64: add kconfig symbol to configure physical address size
247 lines
6.6 KiB
C
247 lines
6.6 KiB
C
/*
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* Based on arch/arm/include/asm/mmu_context.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_MMU_CONTEXT_H
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#define __ASM_MMU_CONTEXT_H
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <linux/sched/hotplug.h>
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#include <linux/mm_types.h>
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#include <asm/cacheflush.h>
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#include <asm/cpufeature.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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#include <asm/cputype.h>
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#include <asm/pgtable.h>
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#include <asm/sysreg.h>
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#include <asm/tlbflush.h>
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static inline void contextidr_thread_switch(struct task_struct *next)
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{
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if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR))
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return;
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write_sysreg(task_pid_nr(next), contextidr_el1);
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isb();
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}
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/*
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* Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
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*/
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static inline void cpu_set_reserved_ttbr0(void)
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{
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unsigned long ttbr = phys_to_ttbr(__pa_symbol(empty_zero_page));
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write_sysreg(ttbr, ttbr0_el1);
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isb();
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}
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static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm)
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{
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BUG_ON(pgd == swapper_pg_dir);
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cpu_set_reserved_ttbr0();
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cpu_do_switch_mm(virt_to_phys(pgd),mm);
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}
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/*
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* TCR.T0SZ value to use when the ID map is active. Usually equals
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* TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
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* physical memory, in which case it will be smaller.
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*/
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extern u64 idmap_t0sz;
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extern u64 idmap_ptrs_per_pgd;
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static inline bool __cpu_uses_extended_idmap(void)
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{
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return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
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unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
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}
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/*
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* True if the extended ID map requires an extra level of translation table
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* to be configured.
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*/
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static inline bool __cpu_uses_extended_idmap_level(void)
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{
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return ARM64_HW_PGTABLE_LEVELS((64 - idmap_t0sz)) > CONFIG_PGTABLE_LEVELS;
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}
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/*
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* Set TCR.T0SZ to its default value (based on VA_BITS)
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*/
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static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
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{
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unsigned long tcr;
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if (!__cpu_uses_extended_idmap())
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return;
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tcr = read_sysreg(tcr_el1);
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tcr &= ~TCR_T0SZ_MASK;
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tcr |= t0sz << TCR_T0SZ_OFFSET;
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write_sysreg(tcr, tcr_el1);
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isb();
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}
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#define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS))
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#define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz)
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/*
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* Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
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*
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* The idmap lives in the same VA range as userspace, but uses global entries
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* and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
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* speculative TLB fetches, we must temporarily install the reserved page
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* tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
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*
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* If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
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* which should not be installed in TTBR0_EL1. In this case we can leave the
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* reserved page tables in place.
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*/
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static inline void cpu_uninstall_idmap(void)
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{
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struct mm_struct *mm = current->active_mm;
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cpu_set_reserved_ttbr0();
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local_flush_tlb_all();
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cpu_set_default_tcr_t0sz();
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if (mm != &init_mm && !system_uses_ttbr0_pan())
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cpu_switch_mm(mm->pgd, mm);
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}
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static inline void cpu_install_idmap(void)
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{
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cpu_set_reserved_ttbr0();
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local_flush_tlb_all();
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cpu_set_idmap_tcr_t0sz();
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cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm);
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}
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/*
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* Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
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* avoiding the possibility of conflicting TLB entries being allocated.
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*/
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static inline void cpu_replace_ttbr1(pgd_t *pgd)
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{
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typedef void (ttbr_replace_func)(phys_addr_t);
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extern ttbr_replace_func idmap_cpu_replace_ttbr1;
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ttbr_replace_func *replace_phys;
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phys_addr_t pgd_phys = virt_to_phys(pgd);
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replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
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cpu_install_idmap();
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replace_phys(pgd_phys);
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cpu_uninstall_idmap();
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}
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/*
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* It would be nice to return ASIDs back to the allocator, but unfortunately
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* that introduces a race with a generation rollover where we could erroneously
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* free an ASID allocated in a future generation. We could workaround this by
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* freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
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* but we'd then need to make sure that we didn't dirty any TLBs afterwards.
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* Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
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* take CPU migration into account.
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*/
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#define destroy_context(mm) do { } while(0)
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void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
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#define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; })
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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static inline void update_saved_ttbr0(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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u64 ttbr;
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if (!system_uses_ttbr0_pan())
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return;
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if (mm == &init_mm)
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ttbr = __pa_symbol(empty_zero_page);
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else
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ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48;
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task_thread_info(tsk)->ttbr0 = ttbr;
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}
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#else
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static inline void update_saved_ttbr0(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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}
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#endif
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static inline void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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/*
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* We don't actually care about the ttbr0 mapping, so point it at the
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* zero page.
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*/
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update_saved_ttbr0(tsk, &init_mm);
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}
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static inline void __switch_mm(struct mm_struct *next)
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{
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unsigned int cpu = smp_processor_id();
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/*
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* init_mm.pgd does not contain any user mappings and it is always
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* active for kernel addresses in TTBR1. Just set the reserved TTBR0.
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*/
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if (next == &init_mm) {
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cpu_set_reserved_ttbr0();
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return;
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}
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check_and_switch_context(next, cpu);
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}
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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if (prev != next)
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__switch_mm(next);
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/*
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* Update the saved TTBR0_EL1 of the scheduled-in task as the previous
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* value may have not been initialised yet (activate_mm caller) or the
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* ASID has changed since the last run (following the context switch
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* of another thread of the same process).
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*/
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update_saved_ttbr0(tsk, next);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) switch_mm(prev, next, current)
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void verify_cpu_asid_bits(void);
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#endif /* !__ASSEMBLY__ */
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#endif /* !__ASM_MMU_CONTEXT_H */
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