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1f27f15258
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
116 lines
3.1 KiB
Plaintext
116 lines
3.1 KiB
Plaintext
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config CLKDEV_LOOKUP
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bool
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select HAVE_CLK
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config HAVE_CLK_PREPARE
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bool
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config HAVE_MACH_CLKDEV
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bool
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config COMMON_CLK
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bool
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select HAVE_CLK_PREPARE
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select CLKDEV_LOOKUP
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---help---
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The common clock framework is a single definition of struct
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clk, useful across many platforms, as well as an
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implementation of the clock API in include/linux/clk.h.
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Architectures utilizing the common struct clk should select
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this option.
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menu "Common Clock Framework"
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depends on COMMON_CLK
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config COMMON_CLK_WM831X
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tristate "Clock driver for WM831x/2x PMICs"
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depends on MFD_WM831X
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---help---
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Supports the clocking subsystem of the WM831x/2x series of
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PMICs from Wolfson Microlectronics.
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config COMMON_CLK_VERSATILE
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bool "Clock driver for ARM Reference designs"
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depends on ARCH_INTEGRATOR || ARCH_REALVIEW || ARCH_VEXPRESS || ARM64
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---help---
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Supports clocking on ARM Reference designs:
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- Integrator/AP and Integrator/CP
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- RealView PB1176, EB, PB11MP and PBX
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- Versatile Express
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config COMMON_CLK_MAX77686
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tristate "Clock driver for Maxim 77686 MFD"
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depends on MFD_MAX77686
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---help---
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This driver supports Maxim 77686 crystal oscillator clock.
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config COMMON_CLK_SI5351
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tristate "Clock driver for SiLabs 5351A/B/C"
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depends on I2C
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select REGMAP_I2C
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select RATIONAL
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---help---
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This driver supports Silicon Labs 5351A/B/C programmable clock
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generators.
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config COMMON_CLK_SI570
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tristate "Clock driver for SiLabs 570 and compatible devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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---help---
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This driver supports Silicon Labs 570/571/598/599 programmable
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clock generators.
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config COMMON_CLK_S2MPS11
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tristate "Clock driver for S2MPS11 MFD"
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depends on MFD_SEC_CORE
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---help---
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This driver supports S2MPS11 crystal oscillator clock.
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config CLK_TWL6040
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tristate "External McPDM functional clock from twl6040"
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depends on TWL6040_CORE
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---help---
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Enable the external functional clock support on OMAP4+ platforms for
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McPDM. McPDM module is using the external bit clock on the McPDM bus
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as functional clock.
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config COMMON_CLK_AXI_CLKGEN
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tristate "AXI clkgen driver"
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depends on ARCH_ZYNQ || MICROBLAZE
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help
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---help---
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Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
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FPGAs. It is commonly used in Analog Devices' reference designs.
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config CLK_PPC_CORENET
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bool "Clock driver for PowerPC corenet platforms"
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depends on PPC_E500MC && OF
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---help---
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This adds the clock driver support for Freescale PowerPC corenet
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platforms using common clock framework.
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config COMMON_CLK_XGENE
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bool "Clock driver for APM XGene SoC"
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default y
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depends on ARM64
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---help---
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Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
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config COMMON_CLK_KEYSTONE
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tristate "Clock drivers for Keystone based SOCs"
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depends on ARCH_KEYSTONE && OF
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---help---
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Supports clock drivers for Keystone based SOCs. These SOCs have local
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a power sleep control module that gate the clock to the IPs and PLLs.
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source "drivers/clk/qcom/Kconfig"
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endmenu
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source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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