mirror of
https://github.com/torvalds/linux.git
synced 2024-11-25 13:41:51 +00:00
9caea00076
Linus noticed odd declaration rules for pci_iounmap() in iomap.h and
pci_iomap.h, where it dependend on either NO_GENERIC_PCI_IOPORT_MAP or
GENERIC_IOMAP when CONFIG_PCI was disabled.
Testing on parisc seems to indicate that we need pci_iounmap() only when
CONFIG_PCI is enabled, so the declaration of pci_iounmap() can be moved
cleanly into pci_iomap.h in sync with the declarations of pci_iomap().
Link: https://lore.kernel.org/all/CAHk-=wjRrh98pZoQ+AzfWmsTZacWxTJKXZ9eKU2X_0+jM=O8nw@mail.gmail.com/
Signed-off-by: Helge Deller <deller@gmx.de>
Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Fixes: 97a29d59fc ("[PARISC] fix compile break caused by iomap: make IOPORT/PCI mapping functions conditional")
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Ulrich Teichert <krypton@ulrich-teichert.org>
Cc: James Bottomley <James.Bottomley@hansenpartnership.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
116 lines
3.9 KiB
C
116 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef __GENERIC_IO_H
|
|
#define __GENERIC_IO_H
|
|
|
|
#include <linux/linkage.h>
|
|
#include <asm/byteorder.h>
|
|
|
|
/*
|
|
* These are the "generic" interfaces for doing new-style
|
|
* memory-mapped or PIO accesses. Architectures may do
|
|
* their own arch-optimized versions, these just act as
|
|
* wrappers around the old-style IO register access functions:
|
|
* read[bwl]/write[bwl]/in[bwl]/out[bwl]
|
|
*
|
|
* Don't include this directly, include it from <asm/io.h>.
|
|
*/
|
|
|
|
/*
|
|
* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
|
|
* access or a MMIO access, these functions don't care. The info is
|
|
* encoded in the hardware mapping set up by the mapping functions
|
|
* (or the cookie itself, depending on implementation and hw).
|
|
*
|
|
* The generic routines just encode the PIO/MMIO as part of the
|
|
* cookie, and coldly assume that the MMIO IO mappings are not
|
|
* in the low address range. Architectures for which this is not
|
|
* true can't use this generic implementation.
|
|
*/
|
|
extern unsigned int ioread8(const void __iomem *);
|
|
extern unsigned int ioread16(const void __iomem *);
|
|
extern unsigned int ioread16be(const void __iomem *);
|
|
extern unsigned int ioread32(const void __iomem *);
|
|
extern unsigned int ioread32be(const void __iomem *);
|
|
#ifdef CONFIG_64BIT
|
|
extern u64 ioread64(const void __iomem *);
|
|
extern u64 ioread64be(const void __iomem *);
|
|
#endif
|
|
|
|
#ifdef readq
|
|
#define ioread64_lo_hi ioread64_lo_hi
|
|
#define ioread64_hi_lo ioread64_hi_lo
|
|
#define ioread64be_lo_hi ioread64be_lo_hi
|
|
#define ioread64be_hi_lo ioread64be_hi_lo
|
|
extern u64 ioread64_lo_hi(const void __iomem *addr);
|
|
extern u64 ioread64_hi_lo(const void __iomem *addr);
|
|
extern u64 ioread64be_lo_hi(const void __iomem *addr);
|
|
extern u64 ioread64be_hi_lo(const void __iomem *addr);
|
|
#endif
|
|
|
|
extern void iowrite8(u8, void __iomem *);
|
|
extern void iowrite16(u16, void __iomem *);
|
|
extern void iowrite16be(u16, void __iomem *);
|
|
extern void iowrite32(u32, void __iomem *);
|
|
extern void iowrite32be(u32, void __iomem *);
|
|
#ifdef CONFIG_64BIT
|
|
extern void iowrite64(u64, void __iomem *);
|
|
extern void iowrite64be(u64, void __iomem *);
|
|
#endif
|
|
|
|
#ifdef writeq
|
|
#define iowrite64_lo_hi iowrite64_lo_hi
|
|
#define iowrite64_hi_lo iowrite64_hi_lo
|
|
#define iowrite64be_lo_hi iowrite64be_lo_hi
|
|
#define iowrite64be_hi_lo iowrite64be_hi_lo
|
|
extern void iowrite64_lo_hi(u64 val, void __iomem *addr);
|
|
extern void iowrite64_hi_lo(u64 val, void __iomem *addr);
|
|
extern void iowrite64be_lo_hi(u64 val, void __iomem *addr);
|
|
extern void iowrite64be_hi_lo(u64 val, void __iomem *addr);
|
|
#endif
|
|
|
|
/*
|
|
* "string" versions of the above. Note that they
|
|
* use native byte ordering for the accesses (on
|
|
* the assumption that IO and memory agree on a
|
|
* byte order, and CPU byteorder is irrelevant).
|
|
*
|
|
* They do _not_ update the port address. If you
|
|
* want MMIO that copies stuff laid out in MMIO
|
|
* memory across multiple ports, use "memcpy_toio()"
|
|
* and friends.
|
|
*/
|
|
extern void ioread8_rep(const void __iomem *port, void *buf, unsigned long count);
|
|
extern void ioread16_rep(const void __iomem *port, void *buf, unsigned long count);
|
|
extern void ioread32_rep(const void __iomem *port, void *buf, unsigned long count);
|
|
|
|
extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);
|
|
extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);
|
|
extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);
|
|
|
|
#ifdef CONFIG_HAS_IOPORT_MAP
|
|
/* Create a virtual mapping cookie for an IO port range */
|
|
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
|
|
extern void ioport_unmap(void __iomem *);
|
|
#endif
|
|
|
|
#ifndef ARCH_HAS_IOREMAP_WC
|
|
#define ioremap_wc ioremap
|
|
#endif
|
|
|
|
#ifndef ARCH_HAS_IOREMAP_WT
|
|
#define ioremap_wt ioremap
|
|
#endif
|
|
|
|
#ifndef ARCH_HAS_IOREMAP_NP
|
|
/* See the comment in asm-generic/io.h about ioremap_np(). */
|
|
#define ioremap_np ioremap_np
|
|
static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
#include <asm-generic/pci_iomap.h>
|
|
|
|
#endif
|