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3179d37ee1
This patch adds code to generate entry & exit code for various low power
states available on systems based around the MIPS Coherent Processing
System architecture (ie. those with a Coherence Manager, Global
Interrupt Controller & for >=CM2 a Cluster Power Controller). States
supported are:
- Non-coherent wait. This state first leaves the coherent domain and
then executes a regular MIPS wait instruction. Power savings are
found from the elimination of coherency interventions between the
core and any other coherent requestors in the system.
- Clock gated. This state leaves the coherent domain and then gates
the clock input to the core. This removes all dynamic power from the
core but leaves the core at the mercy of another to restart its
clock. Register state is preserved, but the core can not service
interrupts whilst its clock is gated.
- Power gated. This deepest state removes all power input to the core.
All register state is lost and the core will restart execution from
its BEV when another core powers it back up. Because register state
is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
implementation in order for the core to exit the state successfully.
The code will detect which states are available on the current system
during boot & generate the entry/exit code for those states. This will
be used by cpuidle & hotplug implementations.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
485 lines
9.0 KiB
ArmAsm
485 lines
9.0 KiB
ArmAsm
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/pm.h>
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#define GCR_CL_COHERENCE_OFS 0x2008
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#define GCR_CL_ID_OFS 0x2028
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.extern mips_cm_base
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.set noreorder
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/*
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* Set dest to non-zero if the core supports the MT ASE, else zero. If
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* MT is not supported then branch to nomt.
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*/
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.macro has_mt dest, nomt
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mfc0 \dest, CP0_CONFIG
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 1
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 2
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bgez \dest, \nomt
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mfc0 \dest, CP0_CONFIG, 3
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andi \dest, \dest, MIPS_CONF3_MT
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beqz \dest, \nomt
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.endm
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.section .text.cps-vec
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.balign 0x1000
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LEAF(mips_cps_core_entry)
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/*
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* These first 8 bytes will be patched by cps_smp_setup to load the
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* base address of the CM GCRs into register v1.
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*/
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.quad 0
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/* Check whether we're here due to an NMI */
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mfc0 k0, CP0_STATUS
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and k0, k0, ST0_NMI
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beqz k0, not_nmi
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nop
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/* This is an NMI */
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la k0, nmi_handler
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jr k0
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nop
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not_nmi:
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/* Setup Cause */
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li t0, CAUSEF_IV
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mtc0 t0, CP0_CAUSE
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/* Setup Status */
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li t0, ST0_CU1 | ST0_CU0
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mtc0 t0, CP0_STATUS
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/*
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* Clear the bits used to index the caches. Note that the architecture
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* dictates that writing to any of TagLo or TagHi selects 0 or 2 should
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* be valid for all MIPS32 CPUs, even those for which said writes are
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* unnecessary.
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*/
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mtc0 zero, CP0_TAGLO, 0
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mtc0 zero, CP0_TAGHI, 0
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mtc0 zero, CP0_TAGLO, 2
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mtc0 zero, CP0_TAGHI, 2
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ehb
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/* Primary cache configuration is indicated by Config1 */
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mfc0 v0, CP0_CONFIG, 1
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/* Detect I-cache line size */
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_EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
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beqz t0, icache_done
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li t1, 2
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sllv t0, t1, t0
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/* Detect I-cache size */
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_EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == I-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
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addi t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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li a0, KSEG0
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add a1, a0, t1
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1: cache Index_Store_Tag_I, 0(a0)
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add a0, a0, t0
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bne a0, a1, 1b
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nop
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icache_done:
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/* Detect D-cache line size */
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_EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
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beqz t0, dcache_done
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li t1, 2
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sllv t0, t1, t0
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/* Detect D-cache size */
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_EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == D-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
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addi t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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li a0, KSEG0
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addu a1, a0, t1
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subu a1, a1, t0
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1: cache Index_Store_Tag_D, 0(a0)
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bne a0, a1, 1b
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add a0, a0, t0
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dcache_done:
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/* Set Kseg0 cacheable, coherent, write-back, write-allocate */
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mfc0 t0, CP0_CONFIG
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ori t0, 0x7
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xori t0, 0x2
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mtc0 t0, CP0_CONFIG
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ehb
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/* Enter the coherent domain */
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li t0, 0xff
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sw t0, GCR_CL_COHERENCE_OFS(v1)
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ehb
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/* Jump to kseg0 */
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la t0, 1f
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jr t0
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nop
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/*
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* We're up, cached & coherent. Perform any further required core-level
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* initialisation.
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*/
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1: jal mips_cps_core_init
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nop
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/*
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* Boot any other VPEs within this core that should be online, and
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* deactivate this VPE if it should be offline.
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*/
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jal mips_cps_boot_vpes
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nop
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/* Off we go! */
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lw t1, VPEBOOTCFG_PC(v0)
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lw gp, VPEBOOTCFG_GP(v0)
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lw sp, VPEBOOTCFG_SP(v0)
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jr t1
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nop
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END(mips_cps_core_entry)
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.org 0x200
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LEAF(excep_tlbfill)
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b .
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nop
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END(excep_tlbfill)
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.org 0x280
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LEAF(excep_xtlbfill)
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b .
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nop
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END(excep_xtlbfill)
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.org 0x300
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LEAF(excep_cache)
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b .
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nop
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END(excep_cache)
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.org 0x380
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LEAF(excep_genex)
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b .
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nop
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END(excep_genex)
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.org 0x400
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LEAF(excep_intex)
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b .
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nop
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END(excep_intex)
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.org 0x480
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LEAF(excep_ejtag)
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la k0, ejtag_debug_handler
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jr k0
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nop
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END(excep_ejtag)
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LEAF(mips_cps_core_init)
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#ifdef CONFIG_MIPS_MT
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/* Check that the core implements the MT ASE */
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has_mt t0, 3f
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nop
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.set push
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.set mt
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/* Only allow 1 TC per VPE to execute... */
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dmt
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/* ...and for the moment only 1 VPE */
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dvpe
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la t1, 1f
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jr.hb t1
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nop
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/* Enter VPE configuration state */
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1: mfc0 t0, CP0_MVPCONTROL
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ori t0, t0, MVPCONTROL_VPC
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mtc0 t0, CP0_MVPCONTROL
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/* Retrieve the number of VPEs within the core */
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mfc0 t0, CP0_MVPCONF0
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srl t0, t0, MVPCONF0_PVPE_SHIFT
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andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
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addi t7, t0, 1
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/* If there's only 1, we're done */
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beqz t0, 2f
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nop
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/* Loop through each VPE within this core */
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li t5, 1
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1: /* Operate on the appropriate TC */
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mtc0 t5, CP0_VPECONTROL
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ehb
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/* Bind TC to VPE (1:1 TC:VPE mapping) */
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mttc0 t5, CP0_TCBIND
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/* Set exclusive TC, non-active, master */
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li t0, VPECONF0_MVP
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sll t1, t5, VPECONF0_XTC_SHIFT
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or t0, t0, t1
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mttc0 t0, CP0_VPECONF0
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/* Set TC non-active, non-allocatable */
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mttc0 zero, CP0_TCSTATUS
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/* Set TC halted */
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li t0, TCHALT_H
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mttc0 t0, CP0_TCHALT
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/* Next VPE */
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addi t5, t5, 1
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slt t0, t5, t7
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bnez t0, 1b
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nop
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/* Leave VPE configuration state */
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2: mfc0 t0, CP0_MVPCONTROL
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xori t0, t0, MVPCONTROL_VPC
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mtc0 t0, CP0_MVPCONTROL
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3: .set pop
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#endif
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jr ra
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nop
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END(mips_cps_core_init)
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LEAF(mips_cps_boot_vpes)
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/* Retrieve CM base address */
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la t0, mips_cm_base
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lw t0, 0(t0)
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/* Calculate a pointer to this cores struct core_boot_config */
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lw t0, GCR_CL_ID_OFS(t0)
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li t1, COREBOOTCFG_SIZE
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mul t0, t0, t1
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la t1, mips_cps_core_bootcfg
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lw t1, 0(t1)
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addu t0, t0, t1
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/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
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has_mt t6, 1f
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li t9, 0
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/* Find the number of VPEs present in the core */
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mfc0 t1, CP0_MVPCONF0
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srl t1, t1, MVPCONF0_PVPE_SHIFT
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andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
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addi t1, t1, 1
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/* Calculate a mask for the VPE ID from EBase.CPUNum */
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clz t1, t1
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li t2, 31
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subu t1, t2, t1
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li t2, 1
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sll t1, t2, t1
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addiu t1, t1, -1
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/* Retrieve the VPE ID from EBase.CPUNum */
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mfc0 t9, $15, 1
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and t9, t9, t1
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1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
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li t1, VPEBOOTCFG_SIZE
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mul v0, t9, t1
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lw t7, COREBOOTCFG_VPECONFIG(t0)
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addu v0, v0, t7
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#ifdef CONFIG_MIPS_MT
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/* If the core doesn't support MT then return */
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bnez t6, 1f
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nop
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jr ra
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nop
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.set push
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.set mt
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1: /* Enter VPE configuration state */
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dvpe
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la t1, 1f
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jr.hb t1
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nop
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1: mfc0 t1, CP0_MVPCONTROL
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ori t1, t1, MVPCONTROL_VPC
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mtc0 t1, CP0_MVPCONTROL
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ehb
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/* Loop through each VPE */
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lw t6, COREBOOTCFG_VPEMASK(t0)
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move t8, t6
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li t5, 0
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/* Check whether the VPE should be running. If not, skip it */
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1: andi t0, t6, 1
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beqz t0, 2f
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nop
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/* Operate on the appropriate TC */
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mfc0 t0, CP0_VPECONTROL
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ori t0, t0, VPECONTROL_TARGTC
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xori t0, t0, VPECONTROL_TARGTC
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or t0, t0, t5
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mtc0 t0, CP0_VPECONTROL
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ehb
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/* Skip the VPE if its TC is not halted */
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mftc0 t0, CP0_TCHALT
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beqz t0, 2f
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nop
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/* Calculate a pointer to the VPEs struct vpe_boot_config */
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li t0, VPEBOOTCFG_SIZE
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mul t0, t0, t5
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addu t0, t0, t7
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/* Set the TC restart PC */
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lw t1, VPEBOOTCFG_PC(t0)
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mttc0 t1, CP0_TCRESTART
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/* Set the TC stack pointer */
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lw t1, VPEBOOTCFG_SP(t0)
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mttgpr t1, sp
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/* Set the TC global pointer */
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lw t1, VPEBOOTCFG_GP(t0)
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mttgpr t1, gp
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/* Copy config from this VPE */
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mfc0 t0, CP0_CONFIG
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mttc0 t0, CP0_CONFIG
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/* Ensure no software interrupts are pending */
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mttc0 zero, CP0_CAUSE
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mttc0 zero, CP0_STATUS
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/* Set TC active, not interrupt exempt */
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mftc0 t0, CP0_TCSTATUS
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li t1, ~TCSTATUS_IXMT
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and t0, t0, t1
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ori t0, t0, TCSTATUS_A
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mttc0 t0, CP0_TCSTATUS
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/* Clear the TC halt bit */
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mttc0 zero, CP0_TCHALT
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/* Set VPE active */
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mftc0 t0, CP0_VPECONF0
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ori t0, t0, VPECONF0_VPA
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mttc0 t0, CP0_VPECONF0
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/* Next VPE */
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2: srl t6, t6, 1
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addi t5, t5, 1
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bnez t6, 1b
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nop
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/* Leave VPE configuration state */
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mfc0 t1, CP0_MVPCONTROL
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xori t1, t1, MVPCONTROL_VPC
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mtc0 t1, CP0_MVPCONTROL
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ehb
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evpe
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/* Check whether this VPE is meant to be running */
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li t0, 1
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sll t0, t0, t9
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and t0, t0, t8
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bnez t0, 2f
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nop
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/* This VPE should be offline, halt the TC */
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li t0, TCHALT_H
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mtc0 t0, CP0_TCHALT
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la t0, 1f
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1: jr.hb t0
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nop
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2: .set pop
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#endif /* CONFIG_MIPS_MT */
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/* Return */
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jr ra
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nop
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END(mips_cps_boot_vpes)
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#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
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/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
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.macro psstate dest
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.set push
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.set noat
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lw $1, TI_CPU(gp)
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sll $1, $1, LONGLOG
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la \dest, __per_cpu_offset
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addu $1, $1, \dest
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lw $1, 0($1)
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la \dest, cps_cpu_state
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addu \dest, \dest, $1
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.set pop
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.endm
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LEAF(mips_cps_pm_save)
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/* Save CPU state */
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SUSPEND_SAVE_REGS
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psstate t1
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SUSPEND_SAVE_STATIC
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jr v0
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nop
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END(mips_cps_pm_save)
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LEAF(mips_cps_pm_restore)
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/* Restore CPU state */
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psstate t1
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RESUME_RESTORE_STATIC
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RESUME_RESTORE_REGS_RETURN
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END(mips_cps_pm_restore)
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#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */
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