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c1fe8d054c
This is one of the last platforms using the old entry path. While this code path is spread over a few files, it is fairly straightforward to convert it into an equivalent C version, leaving the existing algorithm and all the priority handling the same. Unlike most irqchip drivers, this means reading the status register(s) in a loop and always handling the highest-priority irq first. The IOMD_IRQREQC and IOMD_IRQREQD registers are not actaully used here, but I left the code in place for the time being, to keep the conversion as direct as possible. It could be removed in a cleanup on top. Signed-off-by: Arnd Bergmann <arnd@arndb.de> [ardb: drop obsolete IOMD_IRQREQC/IOMD_IRQREQD handling] Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Marc Zyngier <maz@kernel.org> Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
227 lines
6.0 KiB
C
227 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/iomd.h>
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#include <asm/irq.h>
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#include <asm/fiq.h>
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// These are offsets from the stat register for each IRQ bank
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#define STAT 0x00
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#define REQ 0x04
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#define CLR 0x04
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#define MASK 0x08
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static const u8 irq_prio_h[256] = {
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0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
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12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
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14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
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15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
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15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
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};
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static const u8 irq_prio_d[256] = {
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0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16,
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};
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static const u8 irq_prio_l[256] = {
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0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
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4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3,
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6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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};
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static int iomd_get_irq_nr(void)
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{
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int irq;
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u8 reg;
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/* get highest priority first */
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reg = readb(IOC_BASE + IOMD_IRQREQB);
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irq = irq_prio_h[reg];
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if (irq)
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return irq;
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/* get DMA */
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reg = readb(IOC_BASE + IOMD_DMAREQ);
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irq = irq_prio_d[reg];
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if (irq)
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return irq;
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/* get low priority */
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reg = readb(IOC_BASE + IOMD_IRQREQA);
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irq = irq_prio_l[reg];
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if (irq)
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return irq;
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return 0;
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}
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static void iomd_handle_irq(struct pt_regs *regs)
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{
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int irq;
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do {
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irq = iomd_get_irq_nr();
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if (irq)
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generic_handle_irq(irq);
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} while (irq);
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}
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static void __iomem *iomd_get_base(struct irq_data *d)
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{
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void *cd = irq_data_get_irq_chip_data(d);
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return (void __iomem *)(unsigned long)cd;
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}
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static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask)
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{
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struct irq_data *d = irq_get_irq_data(irq);
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d->mask = mask;
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irq_set_chip_data(irq, (void *)(unsigned long)base);
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}
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static void iomd_irq_mask_ack(struct irq_data *d)
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{
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void __iomem *base = iomd_get_base(d);
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unsigned int val, mask = d->mask;
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val = readb(base + MASK);
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writeb(val & ~mask, base + MASK);
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writeb(mask, base + CLR);
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}
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static void iomd_irq_mask(struct irq_data *d)
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{
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void __iomem *base = iomd_get_base(d);
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unsigned int val, mask = d->mask;
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val = readb(base + MASK);
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writeb(val & ~mask, base + MASK);
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}
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static void iomd_irq_unmask(struct irq_data *d)
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{
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void __iomem *base = iomd_get_base(d);
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unsigned int val, mask = d->mask;
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val = readb(base + MASK);
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writeb(val | mask, base + MASK);
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}
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static struct irq_chip iomd_chip_clr = {
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.irq_mask_ack = iomd_irq_mask_ack,
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.irq_mask = iomd_irq_mask,
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.irq_unmask = iomd_irq_unmask,
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};
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static struct irq_chip iomd_chip_noclr = {
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.irq_mask = iomd_irq_mask,
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.irq_unmask = iomd_irq_unmask,
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};
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extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
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void __init rpc_init_irq(void)
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{
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unsigned int irq, clr, set;
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iomd_writeb(0, IOMD_IRQMASKA);
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iomd_writeb(0, IOMD_IRQMASKB);
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iomd_writeb(0, IOMD_FIQMASK);
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iomd_writeb(0, IOMD_DMAMASK);
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set_fiq_handler(&rpc_default_fiq_start,
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&rpc_default_fiq_end - &rpc_default_fiq_start);
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set_handle_irq(iomd_handle_irq);
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for (irq = 0; irq < NR_IRQS; irq++) {
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clr = IRQ_NOREQUEST;
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set = 0;
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if (irq <= 6 || (irq >= 9 && irq <= 15))
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clr |= IRQ_NOPROBE;
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if (irq == 21 || (irq >= 16 && irq <= 19) ||
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irq == IRQ_KEYBOARDTX)
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set |= IRQ_NOAUTOEN;
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switch (irq) {
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case 0 ... 7:
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irq_set_chip_and_handler(irq, &iomd_chip_clr,
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handle_level_irq);
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irq_modify_status(irq, clr, set);
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA,
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BIT(irq));
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break;
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case 8 ... 15:
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irq_set_chip_and_handler(irq, &iomd_chip_noclr,
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handle_level_irq);
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irq_modify_status(irq, clr, set);
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB,
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BIT(irq - 8));
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break;
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case 16 ... 21:
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irq_set_chip_and_handler(irq, &iomd_chip_noclr,
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handle_level_irq);
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irq_modify_status(irq, clr, set);
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT,
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BIT(irq - 16));
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break;
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case 64 ... 71:
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irq_set_chip(irq, &iomd_chip_noclr);
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irq_modify_status(irq, clr, set);
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iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT,
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BIT(irq - 64));
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break;
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}
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}
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init_FIQ(FIQ_START);
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}
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