Peter Zijlstra 1c6c1ca318 mips/atomic: Fix loongson_llsc_mb() wreckage ... The comment describing the loongson_llsc_mb() reorder case doesn't make any sense what so ever. Instruction re-ordering is not an SMP artifact, but rather a CPU local phenomenon. Clarify the comment by explaining that these issue cause a coherence fail. For the branch speculation case; if futex_atomic_cmpxchg_inatomic() needs one at the bne branch target, then surely the normal __cmpxch_asm() implementation does too. We cannot rely on the barriers from cmpxchg() because cmpxchg_local() is implemented with the same macro, and branch prediction and speculation are, too, CPU local. Fixes: e02e07e312 ("MIPS: Loongson: Introduce and use loongson_llsc_mb()") Cc: Huacai Chen <chenhc@lemote.com> Cc: Huang Pei <huangpei@loongson.cn> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Paul Burton <paul.burton@mips.com>		2019-08-31 11:05:17 +01:00
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asm	mips/atomic: Fix loongson_llsc_mb() wreckage	2019-08-31 11:05:17 +01:00
uapi/asm	Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next	2019-06-20 00:06:27 -04:00