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It could be possible that the DMA port differs accross diferent HDMI IPs. Thus, add an IP-specific function to obtain the address offset and size of the DMA data port. Signed-off-by: Ricardo Neri <ricardo.neri@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
191 lines
5.4 KiB
C
191 lines
5.4 KiB
C
/*
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* ti_hdmi.h
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*
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* HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor.
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TI_HDMI_H
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#define _TI_HDMI_H
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struct hdmi_ip_data;
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enum hdmi_pll_pwr {
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HDMI_PLLPWRCMD_ALLOFF = 0,
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HDMI_PLLPWRCMD_PLLONLY = 1,
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HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
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HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
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};
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enum hdmi_core_hdmi_dvi {
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HDMI_DVI = 0,
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HDMI_HDMI = 1
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};
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enum hdmi_clk_refsel {
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HDMI_REFSEL_PCLK = 0,
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HDMI_REFSEL_REF1 = 1,
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HDMI_REFSEL_REF2 = 2,
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HDMI_REFSEL_SYSCLK = 3
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};
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struct hdmi_cm {
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int code;
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int mode;
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};
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struct hdmi_config {
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struct omap_video_timings timings;
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struct hdmi_cm cm;
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};
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/* HDMI PLL structure */
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struct hdmi_pll_info {
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u16 regn;
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u16 regm;
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u32 regmf;
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u16 regm2;
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u16 regsd;
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u16 dcofreq;
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enum hdmi_clk_refsel refsel;
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};
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struct ti_hdmi_ip_ops {
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void (*video_configure)(struct hdmi_ip_data *ip_data);
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int (*phy_enable)(struct hdmi_ip_data *ip_data);
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void (*phy_disable)(struct hdmi_ip_data *ip_data);
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int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len);
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bool (*detect)(struct hdmi_ip_data *ip_data);
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int (*pll_enable)(struct hdmi_ip_data *ip_data);
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void (*pll_disable)(struct hdmi_ip_data *ip_data);
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int (*video_enable)(struct hdmi_ip_data *ip_data);
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void (*video_disable)(struct hdmi_ip_data *ip_data);
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void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
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int (*audio_enable)(struct hdmi_ip_data *ip_data);
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void (*audio_disable)(struct hdmi_ip_data *ip_data);
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int (*audio_start)(struct hdmi_ip_data *ip_data);
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void (*audio_stop)(struct hdmi_ip_data *ip_data);
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int (*audio_config)(struct hdmi_ip_data *ip_data,
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struct omap_dss_audio *audio);
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int (*audio_get_dma_port)(u32 *offset, u32 *size);
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#endif
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};
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/*
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* Refer to section 8.2 in HDMI 1.3 specification for
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* details about infoframe databytes
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*/
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struct hdmi_core_infoframe_avi {
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/* Y0, Y1 rgb,yCbCr */
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u8 db1_format;
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/* A0 Active information Present */
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u8 db1_active_info;
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/* B0, B1 Bar info data valid */
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u8 db1_bar_info_dv;
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/* S0, S1 scan information */
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u8 db1_scan_info;
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/* C0, C1 colorimetry */
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u8 db2_colorimetry;
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/* M0, M1 Aspect ratio (4:3, 16:9) */
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u8 db2_aspect_ratio;
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/* R0...R3 Active format aspect ratio */
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u8 db2_active_fmt_ar;
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/* ITC IT content. */
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u8 db3_itc;
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/* EC0, EC1, EC2 Extended colorimetry */
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u8 db3_ec;
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/* Q1, Q0 Quantization range */
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u8 db3_q_range;
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/* SC1, SC0 Non-uniform picture scaling */
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u8 db3_nup_scaling;
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/* VIC0..6 Video format identification */
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u8 db4_videocode;
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/* PR0..PR3 Pixel repetition factor */
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u8 db5_pixel_repeat;
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/* Line number end of top bar */
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u16 db6_7_line_eoftop;
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/* Line number start of bottom bar */
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u16 db8_9_line_sofbottom;
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/* Pixel number end of left bar */
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u16 db10_11_pixel_eofleft;
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/* Pixel number start of right bar */
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u16 db12_13_pixel_sofright;
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};
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struct hdmi_ip_data {
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void __iomem *base_wp; /* HDMI wrapper */
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unsigned long core_sys_offset;
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unsigned long core_av_offset;
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unsigned long pll_offset;
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unsigned long phy_offset;
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const struct ti_hdmi_ip_ops *ops;
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struct hdmi_config cfg;
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struct hdmi_pll_info pll_data;
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struct hdmi_core_infoframe_avi avi_cfg;
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/* ti_hdmi_4xxx_ip private data. These should be in a separate struct */
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int hpd_gpio;
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struct mutex lock;
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};
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int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
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int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);
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bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data);
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int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data);
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int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
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int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts);
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int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data);
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int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data);
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void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data);
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int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
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struct omap_dss_audio *audio);
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int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size);
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#endif
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#endif
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