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985c0679df
This patch adds support for the ARM generic timers with A64 instructions for accessing the timer registers. It uses the physical counter as the clock source and the virtual counter as sched_clock. The timer frequency can be specified via DT or read from the CNTFRQ_EL0 register. The physical counter is also accessible from user space allowing fast gettimeofday() implementation. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
101 lines
2.3 KiB
C
101 lines
2.3 KiB
C
/*
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* arch/arm64/include/asm/arm_generic.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARM_GENERIC_H
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#define __ASM_ARM_GENERIC_H
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#include <linux/clocksource.h>
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#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
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#define ARCH_TIMER_CTRL_IMASK (1 << 1)
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#define ARCH_TIMER_CTRL_ISTATUS (1 << 2)
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#define ARCH_TIMER_REG_CTRL 0
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#define ARCH_TIMER_REG_FREQ 1
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#define ARCH_TIMER_REG_TVAL 2
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static inline void arch_timer_reg_write(int reg, u32 val)
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{
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("msr cntp_ctl_el0, %0" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
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break;
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default:
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BUILD_BUG();
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}
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isb();
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}
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static inline u32 arch_timer_reg_read(int reg)
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{
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u32 val;
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
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break;
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case ARCH_TIMER_REG_FREQ:
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asm volatile("mrs %0, cntfrq_el0" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
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break;
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default:
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BUILD_BUG();
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}
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return val;
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}
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static inline void __cpuinit arch_counter_enable_user_access(void)
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{
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u32 cntkctl;
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/* Disable user access to the timers and the virtual counter. */
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asm volatile("mrs %0, cntkctl_el1" : "=r" (cntkctl));
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cntkctl &= ~((3 << 8) | (1 << 1));
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/* Enable user access to the physical counter and frequency. */
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cntkctl |= 1;
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asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl));
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}
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static inline cycle_t arch_counter_get_cntpct(void)
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{
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cycle_t cval;
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asm volatile("mrs %0, cntpct_el0" : "=r" (cval));
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return cval;
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}
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static inline cycle_t arch_counter_get_cntvct(void)
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{
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cycle_t cval;
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asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
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return cval;
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}
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#endif
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