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92a11f9e7c
* ->io_base_virt in struct pci_controller is iomem pointer. Marked as such. Most of the places that used it are already annotated to expect iomem. * places that did gratitious (and wrong) casts a-la isa_io_base = (unsigned long)ioremap(...); hose->io_base_virt = (void *)isa_io_base; turned into hose->io_base_virt = ioremap(...); isa_io_base = (unsigned long)hose->io_base_virt; * pci_bus_io_base() annotated as returning iomem pointer. Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
194 lines
6.4 KiB
C
194 lines
6.4 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004 Red Hat, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/immap_cpm2.h>
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#include <asm/mpc8260.h>
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#include "m8260_pci.h"
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/* PCI bus configuration registers.
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*/
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static void __init m8260_setup_pci(struct pci_controller *hose)
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{
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volatile cpm2_map_t *immap = cpm2_immr;
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unsigned long pocmr;
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u16 tempShort;
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#ifndef CONFIG_ATC /* already done in U-Boot */
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/*
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* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
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* and local bus for PCI (SIUMCR [LBPC]).
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*/
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immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;
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#endif
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/* Make PCI lowest priority */
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/* Each 4 bits is a device bus request and the MS 4bits
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is highest priority */
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/* Bus 4bit value
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--- ----------
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CPM high 0b0000
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CPM middle 0b0001
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CPM low 0b0010
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PCI reguest 0b0011
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Reserved 0b0100
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Reserved 0b0101
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Internal Core 0b0110
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External Master 1 0b0111
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External Master 2 0b1000
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External Master 3 0b1001
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The rest are reserved */
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immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
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/* Park bus on core while modifying PCI Bus accesses */
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immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;
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/*
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* Set up master window that allows the CPU to access PCI space. This
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* window is set up using the first SIU PCIBR registers.
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*/
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immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;
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immap->im_memctl.memc_pcibr0 = MPC826x_PCI_BASE | PCIBR_ENABLE;
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/* Disable machine check on no response or target abort */
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immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);
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/* Release PCI RST (by default the PCI RST signal is held low) */
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immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
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/* give it some time */
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mdelay(1);
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/*
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* Set up master window that allows the CPU to access PCI Memory (prefetch)
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* space. This window is set up using the first set of Outbound ATU registers.
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*/
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immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);
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immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - MPC826x_PCI_MEM_OFFSET) >> 12);
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pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 0xfffff;
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immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PREFETCH_EN);
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/*
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* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
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* space. This window is set up using the second set of Outbound ATU registers.
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*/
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immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);
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immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - MPC826x_PCI_MMIO_OFFSET) >> 12);
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pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 0xfffff;
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immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);
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/*
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* Set up master window that allows the CPU to access PCI IO space. This window
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* is set up using the third set of Outbound ATU registers.
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*/
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immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);
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immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);
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pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;
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immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PCI_IO);
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/*
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* Set up slave window that allows PCI masters to access MPC826x local memory.
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* This window is set up using the first set of Inbound ATU registers
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*/
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immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 12);
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immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);
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pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;
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immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | PICMR_PREFETCH_EN);
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/* See above for description - puts PCI request as highest priority */
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immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
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/* Park the bus on the PCI */
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immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
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/* Host mode - specify the bridge as a host-PCI bridge */
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early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_HOST);
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/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);
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early_write_config_word(hose, 0, 0, PCI_COMMAND,
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tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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}
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void __init m8260_find_bridges(void)
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{
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extern int pci_assign_all_busses;
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struct pci_controller * hose;
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pci_assign_all_busses = 1;
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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ppc_md.pci_swizzle = common_swizzle;
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hose->first_busno = 0;
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hose->bus_offset = 0;
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hose->last_busno = 0xff;
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setup_m8260_indirect_pci(hose,
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(unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
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(unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
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m8260_setup_pci(hose);
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hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
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hose->io_base_virt = ioremap(MPC826x_PCI_IO_BASE,
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MPC826x_PCI_IO_SIZE);
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isa_io_base = (unsigned long) hose->io_base_virt;
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/* setup resources */
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pci_init_resource(&hose->mem_resources[0],
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MPC826x_PCI_LOWER_MEM,
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MPC826x_PCI_UPPER_MEM,
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IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
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pci_init_resource(&hose->mem_resources[1],
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MPC826x_PCI_LOWER_MMIO,
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MPC826x_PCI_UPPER_MMIO,
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IORESOURCE_MEM, "PCI memory");
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pci_init_resource(&hose->io_resource,
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MPC826x_PCI_LOWER_IO,
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MPC826x_PCI_UPPER_IO,
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IORESOURCE_IO, "PCI I/O");
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}
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