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df18fedae5
The origianl understanding of clock is wrong. The OTG controller only have one clock input. Passing clock name by pdata is wrong. The clock is defined by device iteself. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
165 lines
4.3 KiB
C
165 lines
4.3 KiB
C
/*
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* Copyright (C) 2011 Marvell International Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MV_USB_OTG_CONTROLLER__
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#define __MV_USB_OTG_CONTROLLER__
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#include <linux/types.h>
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/* Command Register Bit Masks */
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#define USBCMD_RUN_STOP (0x00000001)
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#define USBCMD_CTRL_RESET (0x00000002)
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/* otgsc Register Bit Masks */
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#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
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#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
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#define OTGSC_CTRL_OTG_TERM 0x00000008
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#define OTGSC_CTRL_DATA_PULSING 0x00000010
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#define OTGSC_STS_USB_ID 0x00000100
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#define OTGSC_STS_A_VBUS_VALID 0x00000200
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#define OTGSC_STS_A_SESSION_VALID 0x00000400
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#define OTGSC_STS_B_SESSION_VALID 0x00000800
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#define OTGSC_STS_B_SESSION_END 0x00001000
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#define OTGSC_STS_1MS_TOGGLE 0x00002000
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#define OTGSC_STS_DATA_PULSING 0x00004000
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#define OTGSC_INTSTS_USB_ID 0x00010000
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#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
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#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
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#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
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#define OTGSC_INTSTS_B_SESSION_END 0x00100000
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#define OTGSC_INTSTS_1MS 0x00200000
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#define OTGSC_INTSTS_DATA_PULSING 0x00400000
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#define OTGSC_INTR_USB_ID 0x01000000
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#define OTGSC_INTR_A_VBUS_VALID 0x02000000
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#define OTGSC_INTR_A_SESSION_VALID 0x04000000
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#define OTGSC_INTR_B_SESSION_VALID 0x08000000
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#define OTGSC_INTR_B_SESSION_END 0x10000000
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#define OTGSC_INTR_1MS_TIMER 0x20000000
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#define OTGSC_INTR_DATA_PULSING 0x40000000
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#define CAPLENGTH_MASK (0xff)
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/* Timer's interval, unit 10ms */
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#define T_A_WAIT_VRISE 100
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#define T_A_WAIT_BCON 2000
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#define T_A_AIDL_BDIS 100
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#define T_A_BIDL_ADIS 20
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#define T_B_ASE0_BRST 400
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#define T_B_SE0_SRP 300
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#define T_B_SRP_FAIL 2000
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#define T_B_DATA_PLS 10
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#define T_B_SRP_INIT 100
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#define T_A_SRP_RSPNS 10
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#define T_A_DRV_RSM 5
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enum otg_function {
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OTG_B_DEVICE = 0,
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OTG_A_DEVICE
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};
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enum mv_otg_timer {
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A_WAIT_BCON_TIMER = 0,
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OTG_TIMER_NUM
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};
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/* PXA OTG state machine */
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struct mv_otg_ctrl {
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/* internal variables */
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u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */
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u8 b_srp_done;
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u8 b_hnp_en;
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/* OTG inputs */
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u8 a_bus_drop;
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u8 a_bus_req;
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u8 a_clr_err;
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u8 a_bus_resume;
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u8 a_bus_suspend;
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u8 a_conn;
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u8 a_sess_vld;
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u8 a_srp_det;
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u8 a_vbus_vld;
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u8 b_bus_req; /* B-Device Require Bus */
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u8 b_bus_resume;
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u8 b_bus_suspend;
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u8 b_conn;
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u8 b_se0_srp;
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u8 b_sess_end;
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u8 b_sess_vld;
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u8 id;
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u8 a_suspend_req;
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/*Timer event */
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u8 a_aidl_bdis_timeout;
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u8 b_ase0_brst_timeout;
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u8 a_bidl_adis_timeout;
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u8 a_wait_bcon_timeout;
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struct timer_list timer[OTG_TIMER_NUM];
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};
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#define VUSBHS_MAX_PORTS 8
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struct mv_otg_regs {
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u32 usbcmd; /* Command register */
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u32 usbsts; /* Status register */
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u32 usbintr; /* Interrupt enable */
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u32 frindex; /* Frame index */
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u32 reserved1[1];
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u32 deviceaddr; /* Device Address */
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u32 eplistaddr; /* Endpoint List Address */
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u32 ttctrl; /* HOST TT status and control */
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u32 burstsize; /* Programmable Burst Size */
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u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
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u32 reserved[4];
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u32 epnak; /* Endpoint NAK */
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u32 epnaken; /* Endpoint NAK Enable */
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u32 configflag; /* Configured Flag register */
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u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
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u32 otgsc;
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u32 usbmode; /* USB Host/Device mode */
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u32 epsetupstat; /* Endpoint Setup Status */
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u32 epprime; /* Endpoint Initialize */
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u32 epflush; /* Endpoint De-initialize */
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u32 epstatus; /* Endpoint Status */
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u32 epcomplete; /* Endpoint Interrupt On Complete */
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u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
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u32 mcr; /* Mux Control */
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u32 isr; /* Interrupt Status */
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u32 ier; /* Interrupt Enable */
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};
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struct mv_otg {
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struct usb_phy phy;
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struct mv_otg_ctrl otg_ctrl;
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/* base address */
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void __iomem *phy_regs;
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void __iomem *cap_regs;
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struct mv_otg_regs __iomem *op_regs;
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struct platform_device *pdev;
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int irq;
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u32 irq_status;
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u32 irq_en;
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struct delayed_work work;
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struct workqueue_struct *qwork;
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spinlock_t wq_lock;
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struct mv_usb_platform_data *pdata;
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unsigned int active;
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unsigned int clock_gating;
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struct clk *clk;
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};
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#endif
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