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11daf32be9
At the moment the USB controller's pin muxing is not setup correctly and causes a kernel panic upon system startup, so disable the USB1 device tree node in the MPC5125 tower board dts file. The USB controller is connected to an USB3320 ULPI transceiver and the device tree should receive an update to reflect correct dependencies and required initialization data before the USB1 node can get re-enabled. Signed-off-by: Matteo Facchinetti <matteo.facchinetti@sirius-es.it> Signed-off-by: Anatolij Gustschin <agust@denx.de>
238 lines
5.2 KiB
Plaintext
238 lines
5.2 KiB
Plaintext
/*
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* STx/Freescale ADS5125 MPC5125 silicon
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*
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* Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
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*
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* Reworked by Matteo Facchinetti (engineering@sirius-es.it)
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* Copyright (C) 2013 Sirius Electronic Systems
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "mpc5125twr"; // In BSP "mpc5125ads"
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compatible = "fsl,mpc5125ads", "fsl,mpc5125";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&ipic>;
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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ethernet0 = ð0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5125@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
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bus-frequency = <198000000>; // 198 MHz csb bus
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clock-frequency = <396000000>; // 396 MHz ppc core
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; // 256MB at 0
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};
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sram@30000000 {
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compatible = "fsl,mpc5121-sram";
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reg = <0x30000000 0x08000>; // 32K at 0x30000000
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};
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soc@80000000 {
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compatible = "fsl,mpc5121-immr";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000000 0x400000>;
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reg = <0x80000000 0x400000>;
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bus-frequency = <66000000>; // 66 MHz ips bus
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// IPIC
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// interrupts cell = <intr #, sense>
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// sense values match linux IORESOURCE_IRQ_* defines:
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// sense == 8: Level, low assertion
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// sense == 2: Edge, high-to-low change
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//
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ipic: interrupt-controller@c00 {
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compatible = "fsl,mpc5121-ipic", "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0xc00 0x100>;
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};
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rtc@a00 { // Real time clock
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compatible = "fsl,mpc5121-rtc";
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reg = <0xa00 0x100>;
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interrupts = <79 0x8 80 0x8>;
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};
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reset@e00 { // Reset module
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compatible = "fsl,mpc5125-reset";
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reg = <0xe00 0x100>;
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};
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clock@f00 { // Clock control
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compatible = "fsl,mpc5121-clock";
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reg = <0xf00 0x100>;
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};
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pmc@1000{ // Power Management Controller
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compatible = "fsl,mpc5121-pmc";
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reg = <0x1000 0x100>;
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interrupts = <83 0x2>;
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};
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gpio0: gpio@1100 {
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compatible = "fsl,mpc5125-gpio";
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reg = <0x1100 0x080>;
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interrupts = <78 0x8>;
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};
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gpio1: gpio@1180 {
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compatible = "fsl,mpc5125-gpio";
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reg = <0x1180 0x080>;
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interrupts = <86 0x8>;
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};
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can@1300 { // CAN rev.2
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compatible = "fsl,mpc5121-mscan";
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interrupts = <12 0x8>;
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reg = <0x1300 0x80>;
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};
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can@1380 {
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compatible = "fsl,mpc5121-mscan";
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interrupts = <13 0x8>;
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reg = <0x1380 0x80>;
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};
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sdhc@1500 {
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compatible = "fsl,mpc5121-sdhc";
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interrupts = <8 0x8>;
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reg = <0x1500 0x100>;
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};
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i2c@1700 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1700 0x20>;
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interrupts = <0x9 0x8>;
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};
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i2c@1720 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1720 0x20>;
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interrupts = <0xa 0x8>;
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};
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i2c@1740 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1740 0x20>;
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interrupts = <0xb 0x8>;
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};
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i2ccontrol@1760 {
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compatible = "fsl,mpc5121-i2c-ctrl";
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reg = <0x1760 0x8>;
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};
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diu@2100 {
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compatible = "fsl,mpc5121-diu";
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reg = <0x2100 0x100>;
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interrupts = <64 0x8>;
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};
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mdio@2800 {
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compatible = "fsl,mpc5121-fec-mdio";
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reg = <0x2800 0x800>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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eth0: ethernet@2800 {
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compatible = "fsl,mpc5125-fec";
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reg = <0x2800 0x800>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <4 0x8>;
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phy-handle = < &phy0 >;
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phy-connection-type = "rmii";
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};
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// IO control
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ioctl@a000 {
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compatible = "fsl,mpc5125-ioctl";
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reg = <0xA000 0x1000>;
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};
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// disable USB1 port
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// TODO:
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// correct pinmux config and fix USB3320 ulpi dependency
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// before re-enabling it
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usb@3000 {
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compatible = "fsl,mpc5121-usb2-dr";
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reg = <0x3000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <43 0x8>;
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dr_mode = "host";
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phy_type = "ulpi";
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status = "disabled";
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};
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// 5125 PSCs are not 52xx or 5121 PSC compatible
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// PSC1 uart0 aka ttyPSC0
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serial@11100 {
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compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
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reg = <0x11100 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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// PSC9 uart1 aka ttyPSC1
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serial@11900 {
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compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
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reg = <0x11900 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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pscfifo@11f00 {
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compatible = "fsl,mpc5121-psc-fifo";
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reg = <0x11f00 0x100>;
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interrupts = <40 0x8>;
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};
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dma@14000 {
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compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
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reg = <0x14000 0x1800>;
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interrupts = <65 0x8>;
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};
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};
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};
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