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During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com> |
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ast_dp501.c | ||
ast_dram_tables.h | ||
ast_drv.c | ||
ast_drv.h | ||
ast_fb.c | ||
ast_main.c | ||
ast_mode.c | ||
ast_post.c | ||
ast_tables.h | ||
ast_ttm.c | ||
Kconfig | ||
Makefile |