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865499ea90
Looks like our L_PTE_S2_RDWR definition is slightly wrong, and is actually write only (see ARM ARM Table B3-9, Stage 2 control of access permissions). Didn't make a difference for normal pages, as we OR the flags together, but I'm still wondering how it worked for Stage-2 mapped devices, such as the GIC. Brown paper bag time, again. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
174 lines
5.6 KiB
C
174 lines
5.6 KiB
C
/*
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* arch/arm/include/asm/pgtable-3level.h
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*
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_PGTABLE_3LEVEL_H
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#define _ASM_PGTABLE_3LEVEL_H
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/*
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* With LPAE, there are 3 levels of page tables. Each level has 512 entries of
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* 8 bytes each, occupying a 4K page. The first level table covers a range of
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* 512GB, each entry representing 1GB. Since we are limited to 4GB input
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* address range, only 4 entries in the PGD are used.
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*
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* There are enough spare bits in a page table entry for the kernel specific
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* state.
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*/
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#define PTRS_PER_PTE 512
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#define PTRS_PER_PMD 512
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#define PTRS_PER_PGD 4
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#define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
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#define PTE_HWTABLE_OFF (0)
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#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map.
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*/
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#define PGDIR_SHIFT 30
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/*
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* PMD_SHIFT determines the size a middle-level page table entry can map.
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*/
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#define PMD_SHIFT 21
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* section address mask and size definitions.
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*/
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#define SECTION_SHIFT 21
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#define SECTION_SIZE (1UL << SECTION_SHIFT)
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#define SECTION_MASK (~(SECTION_SIZE-1))
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#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
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/*
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* "Linux" PTE definitions for LPAE.
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*
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* These bits overlap with the hardware bits but the naming is preserved for
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* consistency with the classic page table format.
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*/
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#define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
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#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */
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#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
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#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
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#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
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#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
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#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
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#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */
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#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */
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#define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
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/*
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* To be used in assembly code with the upper page attributes.
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*/
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#define L_PTE_XN_HIGH (1 << (54 - 32))
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#define L_PTE_DIRTY_HIGH (1 << (55 - 32))
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
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#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
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#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
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#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
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#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
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#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
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#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
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#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
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#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
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#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
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/*
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* Software PGD flags.
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*/
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#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
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/*
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* 2nd stage PTE definitions for LPAE.
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*/
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#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
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#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
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#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
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#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
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#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
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/*
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* Hyp-mode PL2 PTE definitions for LPAE.
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*/
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#define L_PTE_HYP L_PTE_USER
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#ifndef __ASSEMBLY__
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#define pud_none(pud) (!pud_val(pud))
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#define pud_bad(pud) (!(pud_val(pud) & 2))
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#define pud_present(pud) (pud_val(pud))
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#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
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PMD_TYPE_TABLE)
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#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
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PMD_TYPE_SECT)
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#define pud_clear(pudp) \
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do { \
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*pudp = __pud(0); \
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clean_pmd_entry(pudp); \
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} while (0)
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#define set_pud(pudp, pud) \
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do { \
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*pudp = pud; \
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flush_pmd_entry(pudp); \
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} while (0)
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static inline pmd_t *pud_page_vaddr(pud_t pud)
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{
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return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
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}
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/* Find an entry in the second-level page table.. */
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#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
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static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
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{
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return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
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}
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#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
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#define copy_pmd(pmdpd,pmdps) \
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do { \
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*pmdpd = *pmdps; \
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flush_pmd_entry(pmdpd); \
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} while (0)
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#define pmd_clear(pmdp) \
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do { \
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*pmdp = __pmd(0); \
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clean_pmd_entry(pmdp); \
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} while (0)
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#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_PGTABLE_3LEVEL_H */
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