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688c50aa72
As we are about to be lazy with saving and restoring the timer registers, we prepare by moving all possible timer configuration logic out of the hyp code. All virtual timer registers can be programmed from EL1 and since the arch timer is always a level triggered interrupt we can safely do this with interrupts disabled in the host kernel on the way to the guest without taking vtimer interrupts in the host kernel (yet). The downside is that the cntvoff register can only be programmed from hyp mode, so we jump into hyp mode and back to program it. This is also safe, because the host kernel doesn't use the virtual timer in the KVM code. It may add a little performance performance penalty, but only until following commits where we move this operation to vcpu load/put. Signed-off-by: Christoffer Dall <cdall@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
85 lines
2.9 KiB
C
85 lines
2.9 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_ASM_H__
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#define __ARM_KVM_ASM_H__
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#include <asm/virt.h>
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#define ARM_EXIT_WITH_ABORT_BIT 31
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#define ARM_EXCEPTION_CODE(x) ((x) & ~(1U << ARM_EXIT_WITH_ABORT_BIT))
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#define ARM_ABORT_PENDING(x) !!((x) & (1U << ARM_EXIT_WITH_ABORT_BIT))
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#define ARM_EXCEPTION_RESET 0
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#define ARM_EXCEPTION_UNDEFINED 1
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#define ARM_EXCEPTION_SOFTWARE 2
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#define ARM_EXCEPTION_PREF_ABORT 3
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#define ARM_EXCEPTION_DATA_ABORT 4
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#define ARM_EXCEPTION_IRQ 5
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#define ARM_EXCEPTION_FIQ 6
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#define ARM_EXCEPTION_HVC 7
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#define ARM_EXCEPTION_HYP_GONE HVC_STUB_ERR
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/*
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* The rr_lo_hi macro swaps a pair of registers depending on
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* current endianness. It is used in conjunction with ldrd and strd
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* instructions that load/store a 64-bit value from/to memory to/from
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* a pair of registers which are used with the mrrc and mcrr instructions.
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* If used with the ldrd/strd instructions, the a1 parameter is the first
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* source/destination register and the a2 parameter is the second
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* source/destination register. Note that the ldrd/strd instructions
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* already swap the bytes within the words correctly according to the
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* endianness setting, but the order of the registers need to be effectively
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* swapped when used with the mrrc/mcrr instructions.
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*/
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#define rr_lo_hi(a1, a2) a2, a1
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#else
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#define rr_lo_hi(a1, a2) a1, a2
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#endif
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#define kvm_ksym_ref(kva) (kva)
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#ifndef __ASSEMBLY__
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struct kvm;
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struct kvm_vcpu;
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extern char __kvm_hyp_init[];
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extern char __kvm_hyp_init_end[];
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extern char __kvm_hyp_vector[];
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extern void __kvm_flush_vm_context(void);
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extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
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extern void __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu);
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extern void __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high);
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extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
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extern void __init_stage2_translation(void);
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extern u64 __vgic_v3_get_ich_vtr_el2(void);
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extern u64 __vgic_v3_read_vmcr(void);
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extern void __vgic_v3_write_vmcr(u32 vmcr);
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extern void __vgic_v3_init_lrs(void);
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#endif
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#endif /* __ARM_KVM_ASM_H__ */
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