Vincent Chen 1a0e5dbd37 riscv: sifive: Add SiFive alternative ports ... Add required ports of the Alternative scheme for SiFive. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-04-26 08:24:56 -07:00
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boot	RISC-V Patches for the 5.12 Merge Window	2021-02-26 10:28:35 -08:00
configs	RISC-V: Enable CPU Hotplug in defconfigs	2021-02-26 21:24:02 -08:00
errata	riscv: sifive: Add SiFive alternative ports	2021-04-26 08:24:56 -07:00
include	riscv: sifive: Add SiFive alternative ports	2021-04-26 08:24:56 -07:00
kernel	riscv: Introduce alternative mechanism to apply errata solution	2021-04-26 08:24:55 -07:00
lib	riscv: Add support for function error injection	2021-01-14 15:09:09 -08:00
mm	riscv: Cleanup KASAN_VMALLOC support	2021-03-29 23:13:29 -07:00
net	bpf: Rename BPF_XADD and prepare to encode other atomics in .imm	2021-01-14 18:34:29 -08:00
Kbuild	riscv: Allow device trees to be built into the kernel	2020-05-18 11:38:05 -07:00
Kconfig	riscv: Introduce alternative mechanism to apply errata solution	2021-04-26 08:24:55 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.erratas	riscv: sifive: Add SiFive alternative ports	2021-04-26 08:24:56 -07:00
Kconfig.socs	riscv: sifive: Add SiFive alternative ports	2021-04-26 08:24:56 -07:00
Makefile	riscv: Introduce alternative mechanism to apply errata solution	2021-04-26 08:24:55 -07:00