mirror of
https://github.com/torvalds/linux.git
synced 2024-12-14 23:25:54 +00:00
2b45e0f9f3
Merge in the x86 changes to apply a fix. Signed-off-by: Ingo Molnar <mingo@kernel.org>
914 lines
22 KiB
C
914 lines
22 KiB
C
#include <linux/export.h>
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#include <linux/bitops.h>
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#include <linux/elf.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/apic.h>
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#include <asm/cpu.h>
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#include <asm/pci-direct.h>
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#ifdef CONFIG_X86_64
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# include <asm/mmconfig.h>
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# include <asm/cacheflush.h>
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#endif
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#include "cpu.h"
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static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
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{
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u32 gprs[8] = { 0 };
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int err;
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WARN_ONCE((boot_cpu_data.x86 != 0xf),
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"%s should only be used on K8!\n", __func__);
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gprs[1] = msr;
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gprs[7] = 0x9c5a203a;
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err = rdmsr_safe_regs(gprs);
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*p = gprs[0] | ((u64)gprs[2] << 32);
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return err;
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}
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static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
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{
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u32 gprs[8] = { 0 };
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WARN_ONCE((boot_cpu_data.x86 != 0xf),
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"%s should only be used on K8!\n", __func__);
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gprs[0] = (u32)val;
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gprs[1] = msr;
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gprs[2] = val >> 32;
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gprs[7] = 0x9c5a203a;
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return wrmsr_safe_regs(gprs);
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}
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#ifdef CONFIG_X86_32
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/*
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* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
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* misexecution of code under Linux. Owners of such processors should
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* contact AMD for precise details and a CPU swap.
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*
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* See http://www.multimania.com/poulot/k6bug.html
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* and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
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* (Publication # 21266 Issue Date: August 1998)
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*
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* The following test is erm.. interesting. AMD neglected to up
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* the chip setting when fixing the bug but they also tweaked some
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* performance at the same time..
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*/
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extern __visible void vide(void);
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__asm__(".globl vide\n\t.align 4\nvide: ret");
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static void init_amd_k5(struct cpuinfo_x86 *c)
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{
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/*
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* General Systems BIOSen alias the cpu frequency registers
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* of the Elan at 0x000df000. Unfortuantly, one of the Linux
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* drivers subsequently pokes it, and changes the CPU speed.
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* Workaround : Remove the unneeded alias.
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*/
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#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
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#define CBAR_ENB (0x80000000)
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#define CBAR_KEY (0X000000CB)
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if (c->x86_model == 9 || c->x86_model == 10) {
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if (inl(CBAR) & CBAR_ENB)
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outl(0 | CBAR_KEY, CBAR);
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}
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}
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static void init_amd_k6(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
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if (c->x86_model < 6) {
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/* Based on AMD doc 20734R - June 2000 */
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if (c->x86_model == 0) {
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clear_cpu_cap(c, X86_FEATURE_APIC);
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set_cpu_cap(c, X86_FEATURE_PGE);
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}
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return;
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}
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if (c->x86_model == 6 && c->x86_mask == 1) {
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const int K6_BUG_LOOP = 1000000;
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int n;
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void (*f_vide)(void);
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unsigned long d, d2;
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printk(KERN_INFO "AMD K6 stepping B detected - ");
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/*
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* It looks like AMD fixed the 2.6.2 bug and improved indirect
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* calls at the same time.
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*/
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n = K6_BUG_LOOP;
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f_vide = vide;
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rdtscl(d);
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while (n--)
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f_vide();
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rdtscl(d2);
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d = d2-d;
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if (d > 20*K6_BUG_LOOP)
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printk(KERN_CONT
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"system stability may be impaired when more than 32 MB are used.\n");
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else
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printk(KERN_CONT "probably OK (after B9730xxxx).\n");
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}
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/* K6 with old style WHCR */
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if (c->x86_model < 8 ||
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(c->x86_model == 8 && c->x86_mask < 8)) {
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/* We can only write allocate on the low 508Mb */
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if (mbytes > 508)
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mbytes = 508;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0x0000FFFF) == 0) {
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unsigned long flags;
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l = (1<<0)|((mbytes/4)<<1);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
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mbytes);
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}
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return;
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}
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if ((c->x86_model == 8 && c->x86_mask > 7) ||
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c->x86_model == 9 || c->x86_model == 13) {
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/* The more serious chips .. */
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if (mbytes > 4092)
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mbytes = 4092;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0xFFFF0000) == 0) {
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unsigned long flags;
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l = ((mbytes>>2)<<22)|(1<<16);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
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mbytes);
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}
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return;
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}
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if (c->x86_model == 10) {
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/* AMD Geode LX is model 10 */
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/* placeholder for any needed mods */
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return;
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}
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}
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static void amd_k7_smp_check(struct cpuinfo_x86 *c)
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{
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/* calling is from identify_secondary_cpu() ? */
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if (!c->cpu_index)
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return;
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/*
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* Certain Athlons might work (for various values of 'work') in SMP
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* but they are not certified as MP capable.
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*/
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/* Athlon 660/661 is valid. */
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if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
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(c->x86_mask == 1)))
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return;
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/* Duron 670 is valid */
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if ((c->x86_model == 7) && (c->x86_mask == 0))
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return;
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/*
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* Athlon 662, Duron 671, and Athlon >model 7 have capability
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* bit. It's worth noting that the A5 stepping (662) of some
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* Athlon XP's have the MP bit set.
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
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* more.
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*/
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if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
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((c->x86_model == 7) && (c->x86_mask >= 1)) ||
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(c->x86_model > 7))
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if (cpu_has_mp)
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return;
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/* If we get here, not a certified SMP capable AMD system. */
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/*
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* Don't taint if we are running SMP kernel on a single non-MP
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* approved Athlon
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*/
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WARN_ONCE(1, "WARNING: This combination of AMD"
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" processors is not suitable for SMP.\n");
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add_taint(TAINT_UNSAFE_SMP, LOCKDEP_NOW_UNRELIABLE);
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}
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static void init_amd_k7(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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/*
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* Bit 15 of Athlon specific MSR 15, needs to be 0
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* to enable SSE on Palomino/Morgan/Barton CPU's.
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* If the BIOS didn't enable it already, enable it here.
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*/
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if (c->x86_model >= 6 && c->x86_model <= 10) {
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if (!cpu_has(c, X86_FEATURE_XMM)) {
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printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
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rdmsr(MSR_K7_HWCR, l, h);
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l &= ~0x00008000;
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wrmsr(MSR_K7_HWCR, l, h);
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set_cpu_cap(c, X86_FEATURE_XMM);
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}
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}
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/*
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* It's been determined by AMD that Athlons since model 8 stepping 1
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* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
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* As per AMD technical note 27212 0.2
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*/
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if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
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rdmsr(MSR_K7_CLK_CTL, l, h);
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if ((l & 0xfff00000) != 0x20000000) {
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printk(KERN_INFO
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"CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
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l, ((l & 0x000fffff)|0x20000000));
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wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
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}
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}
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set_cpu_cap(c, X86_FEATURE_K7);
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amd_k7_smp_check(c);
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}
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#endif
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#ifdef CONFIG_NUMA
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/*
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* To workaround broken NUMA config. Read the comment in
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* srat_detect_node().
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*/
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static int nearby_node(int apicid)
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{
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int i, node;
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for (i = apicid - 1; i >= 0; i--) {
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node = __apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
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node = __apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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return first_node(node_online_map); /* Shouldn't happen */
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}
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#endif
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/*
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* Fixup core topology information for
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* (1) AMD multi-node processors
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* Assumption: Number of cores in each internal node is the same.
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* (2) AMD processors supporting compute units
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*/
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#ifdef CONFIG_X86_HT
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static void amd_get_topology(struct cpuinfo_x86 *c)
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{
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u32 nodes, cores_per_cu = 1;
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u8 node_id;
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int cpu = smp_processor_id();
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/* get information required for multi-node processors */
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if (cpu_has_topoext) {
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u32 eax, ebx, ecx, edx;
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cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
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nodes = ((ecx >> 8) & 7) + 1;
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node_id = ecx & 7;
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/* get compute unit information */
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smp_num_siblings = ((ebx >> 8) & 3) + 1;
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c->compute_unit_id = ebx & 0xff;
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cores_per_cu += ((ebx >> 8) & 3);
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} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
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u64 value;
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rdmsrl(MSR_FAM10H_NODE_ID, value);
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nodes = ((value >> 3) & 7) + 1;
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node_id = value & 7;
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} else
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return;
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/* fixup multi-node processor information */
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if (nodes > 1) {
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u32 cores_per_node;
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u32 cus_per_node;
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set_cpu_cap(c, X86_FEATURE_AMD_DCM);
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cores_per_node = c->x86_max_cores / nodes;
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cus_per_node = cores_per_node / cores_per_cu;
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/* store NodeID, use llc_shared_map to store sibling info */
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per_cpu(cpu_llc_id, cpu) = node_id;
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/* core id has to be in the [0 .. cores_per_node - 1] range */
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c->cpu_core_id %= cores_per_node;
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c->compute_unit_id %= cus_per_node;
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}
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}
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#endif
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/*
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* On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
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* Assumes number of cores is a power of two.
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*/
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static void amd_detect_cmp(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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unsigned bits;
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int cpu = smp_processor_id();
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bits = c->x86_coreid_bits;
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/* Low order bits define the core id (index of core in socket) */
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c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
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/* Convert the initial APIC ID into the socket ID */
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c->phys_proc_id = c->initial_apicid >> bits;
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/* use socket ID also for last level cache */
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per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
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amd_get_topology(c);
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#endif
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}
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u16 amd_get_nb_id(int cpu)
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{
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u16 id = 0;
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#ifdef CONFIG_SMP
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id = per_cpu(cpu_llc_id, cpu);
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#endif
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return id;
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}
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EXPORT_SYMBOL_GPL(amd_get_nb_id);
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static void srat_detect_node(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_NUMA
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int cpu = smp_processor_id();
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int node;
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unsigned apicid = c->apicid;
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node = numa_cpu_node(cpu);
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if (node == NUMA_NO_NODE)
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node = per_cpu(cpu_llc_id, cpu);
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/*
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* On multi-fabric platform (e.g. Numascale NumaChip) a
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* platform-specific handler needs to be called to fixup some
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* IDs of the CPU.
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*/
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if (x86_cpuinit.fixup_cpu_id)
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x86_cpuinit.fixup_cpu_id(c, node);
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if (!node_online(node)) {
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/*
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* Two possibilities here:
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*
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* - The CPU is missing memory and no node was created. In
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* that case try picking one from a nearby CPU.
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*
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* - The APIC IDs differ from the HyperTransport node IDs
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* which the K8 northbridge parsing fills in. Assume
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* they are all increased by a constant offset, but in
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* the same order as the HT nodeids. If that doesn't
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* result in a usable node fall back to the path for the
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* previous case.
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*
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* This workaround operates directly on the mapping between
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* APIC ID and NUMA node, assuming certain relationship
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* between APIC ID, HT node ID and NUMA topology. As going
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* through CPU mapping may alter the outcome, directly
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* access __apicid_to_node[].
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*/
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int ht_nodeid = c->initial_apicid;
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if (ht_nodeid >= 0 &&
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__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
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node = __apicid_to_node[ht_nodeid];
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/* Pick a nearby node */
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if (!node_online(node))
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node = nearby_node(apicid);
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}
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numa_set_node(cpu, node);
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#endif
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}
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static void early_init_amd_mc(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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unsigned bits, ecx;
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/* Multi core CPU? */
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if (c->extended_cpuid_level < 0x80000008)
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return;
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ecx = cpuid_ecx(0x80000008);
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c->x86_max_cores = (ecx & 0xff) + 1;
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/* CPU telling us the core id bits shift? */
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bits = (ecx >> 12) & 0xF;
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/* Otherwise recompute */
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if (bits == 0) {
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while ((1 << bits) < c->x86_max_cores)
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bits++;
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}
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c->x86_coreid_bits = bits;
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#endif
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}
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static void bsp_init_amd(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
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if (c->x86 > 0x10 ||
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(c->x86 == 0x10 && c->x86_model >= 0x2)) {
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u64 val;
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rdmsrl(MSR_K7_HWCR, val);
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if (!(val & BIT(24)))
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printk(KERN_WARNING FW_BUG "TSC doesn't count "
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"with P0 frequency!\n");
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}
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}
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if (c->x86 == 0x15) {
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unsigned long upperbit;
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u32 cpuid, assoc;
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cpuid = cpuid_edx(0x80000005);
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assoc = cpuid >> 16 & 0xff;
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upperbit = ((cpuid >> 24) << 10) / assoc;
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va_align.mask = (upperbit - 1) & PAGE_MASK;
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va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
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}
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}
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static void early_init_amd(struct cpuinfo_x86 *c)
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{
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early_init_amd_mc(c);
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/*
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* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
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* with P/T states and does not stop in deep C-states
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*/
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if (c->x86_power & (1 << 8)) {
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
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if (!check_tsc_unstable())
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set_sched_clock_stable();
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}
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|
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSCALL32);
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|
#else
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/* Set MTRR capability flag if appropriate */
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|
if (c->x86 == 5)
|
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if (c->x86_model == 13 || c->x86_model == 9 ||
|
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(c->x86_model == 8 && c->x86_mask >= 8))
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set_cpu_cap(c, X86_FEATURE_K6_MTRR);
|
|
#endif
|
|
#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
|
|
/* check CPU config space for extended APIC ID */
|
|
if (cpu_has_apic && c->x86 >= 0xf) {
|
|
unsigned int val;
|
|
val = read_pci_config(0, 24, 0, 0x68);
|
|
if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
|
|
set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
|
|
}
|
|
#endif
|
|
|
|
/* F16h erratum 793, CVE-2013-6885 */
|
|
if (c->x86 == 0x16 && c->x86_model <= 0xf) {
|
|
u64 val;
|
|
|
|
rdmsrl(MSR_AMD64_LS_CFG, val);
|
|
if (!(val & BIT(15)))
|
|
wrmsrl(MSR_AMD64_LS_CFG, val | BIT(15));
|
|
}
|
|
|
|
}
|
|
|
|
static const int amd_erratum_383[];
|
|
static const int amd_erratum_400[];
|
|
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
|
|
|
|
static void init_amd(struct cpuinfo_x86 *c)
|
|
{
|
|
u32 dummy;
|
|
unsigned long long value;
|
|
|
|
#ifdef CONFIG_SMP
|
|
/*
|
|
* Disable TLB flush filter by setting HWCR.FFDIS on K8
|
|
* bit 6 of msr C001_0015
|
|
*
|
|
* Errata 63 for SH-B3 steppings
|
|
* Errata 122 for all steppings (F+ have it disabled by default)
|
|
*/
|
|
if (c->x86 == 0xf) {
|
|
rdmsrl(MSR_K7_HWCR, value);
|
|
value |= 1 << 6;
|
|
wrmsrl(MSR_K7_HWCR, value);
|
|
}
|
|
#endif
|
|
|
|
early_init_amd(c);
|
|
|
|
/*
|
|
* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
|
|
* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
|
|
*/
|
|
clear_cpu_cap(c, 0*32+31);
|
|
|
|
#ifdef CONFIG_X86_64
|
|
/* On C+ stepping K8 rep microcode works well for copy/memset */
|
|
if (c->x86 == 0xf) {
|
|
u32 level;
|
|
|
|
level = cpuid_eax(1);
|
|
if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
|
|
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
|
|
|
|
/*
|
|
* Some BIOSes incorrectly force this feature, but only K8
|
|
* revision D (model = 0x14) and later actually support it.
|
|
* (AMD Erratum #110, docId: 25759).
|
|
*/
|
|
if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
|
|
clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
|
|
if (!rdmsrl_amd_safe(0xc001100d, &value)) {
|
|
value &= ~(1ULL << 32);
|
|
wrmsrl_amd_safe(0xc001100d, value);
|
|
}
|
|
}
|
|
|
|
}
|
|
if (c->x86 >= 0x10)
|
|
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
|
|
|
|
/* get apicid instead of initial apic id from cpuid */
|
|
c->apicid = hard_smp_processor_id();
|
|
#else
|
|
|
|
/*
|
|
* FIXME: We should handle the K5 here. Set up the write
|
|
* range and also turn on MSR 83 bits 4 and 31 (write alloc,
|
|
* no bus pipeline)
|
|
*/
|
|
|
|
switch (c->x86) {
|
|
case 4:
|
|
init_amd_k5(c);
|
|
break;
|
|
case 5:
|
|
init_amd_k6(c);
|
|
break;
|
|
case 6: /* An Athlon/Duron */
|
|
init_amd_k7(c);
|
|
break;
|
|
}
|
|
|
|
/* K6s reports MCEs but don't actually have all the MSRs */
|
|
if (c->x86 < 6)
|
|
clear_cpu_cap(c, X86_FEATURE_MCE);
|
|
#endif
|
|
|
|
/* Enable workaround for FXSAVE leak */
|
|
if (c->x86 >= 6)
|
|
set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
|
|
|
|
if (!c->x86_model_id[0]) {
|
|
switch (c->x86) {
|
|
case 0xf:
|
|
/* Should distinguish Models here, but this is only
|
|
a fallback anyways. */
|
|
strcpy(c->x86_model_id, "Hammer");
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* re-enable TopologyExtensions if switched off by BIOS */
|
|
if ((c->x86 == 0x15) &&
|
|
(c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
|
|
!cpu_has(c, X86_FEATURE_TOPOEXT)) {
|
|
|
|
if (!rdmsrl_safe(0xc0011005, &value)) {
|
|
value |= 1ULL << 54;
|
|
wrmsrl_safe(0xc0011005, value);
|
|
rdmsrl(0xc0011005, value);
|
|
if (value & (1ULL << 54)) {
|
|
set_cpu_cap(c, X86_FEATURE_TOPOEXT);
|
|
printk(KERN_INFO FW_INFO "CPU: Re-enabling "
|
|
"disabled Topology Extensions Support\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The way access filter has a performance penalty on some workloads.
|
|
* Disable it on the affected CPUs.
|
|
*/
|
|
if ((c->x86 == 0x15) &&
|
|
(c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
|
|
|
|
if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
|
|
value |= 0x1E;
|
|
wrmsrl_safe(0xc0011021, value);
|
|
}
|
|
}
|
|
|
|
cpu_detect_cache_sizes(c);
|
|
|
|
/* Multi core CPU? */
|
|
if (c->extended_cpuid_level >= 0x80000008) {
|
|
amd_detect_cmp(c);
|
|
srat_detect_node(c);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_32
|
|
detect_ht(c);
|
|
#endif
|
|
|
|
init_amd_cacheinfo(c);
|
|
|
|
if (c->x86 >= 0xf)
|
|
set_cpu_cap(c, X86_FEATURE_K8);
|
|
|
|
if (cpu_has_xmm2) {
|
|
/* MFENCE stops RDTSC speculation */
|
|
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
if (c->x86 == 0x10) {
|
|
/* do this for boot cpu */
|
|
if (c == &boot_cpu_data)
|
|
check_enable_amd_mmconf_dmi();
|
|
|
|
fam10h_check_enable_mmcfg();
|
|
}
|
|
|
|
if (c == &boot_cpu_data && c->x86 >= 0xf) {
|
|
unsigned long long tseg;
|
|
|
|
/*
|
|
* Split up direct mapping around the TSEG SMM area.
|
|
* Don't do it for gbpages because there seems very little
|
|
* benefit in doing so.
|
|
*/
|
|
if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
|
|
unsigned long pfn = tseg >> PAGE_SHIFT;
|
|
|
|
printk(KERN_DEBUG "tseg: %010llx\n", tseg);
|
|
if (pfn_range_is_mapped(pfn, pfn + 1))
|
|
set_memory_4k((unsigned long)__va(tseg), 1);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Family 0x12 and above processors have APIC timer
|
|
* running in deep C states.
|
|
*/
|
|
if (c->x86 > 0x11)
|
|
set_cpu_cap(c, X86_FEATURE_ARAT);
|
|
|
|
if (c->x86 == 0x10) {
|
|
/*
|
|
* Disable GART TLB Walk Errors on Fam10h. We do this here
|
|
* because this is always needed when GART is enabled, even in a
|
|
* kernel which has no MCE support built in.
|
|
* BIOS should disable GartTlbWlk Errors themself. If
|
|
* it doesn't do it here as suggested by the BKDG.
|
|
*
|
|
* Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
|
|
*/
|
|
u64 mask;
|
|
int err;
|
|
|
|
err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
|
|
if (err == 0) {
|
|
mask |= (1 << 10);
|
|
wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
|
|
}
|
|
|
|
/*
|
|
* On family 10h BIOS may not have properly enabled WC+ support,
|
|
* causing it to be converted to CD memtype. This may result in
|
|
* performance degradation for certain nested-paging guests.
|
|
* Prevent this conversion by clearing bit 24 in
|
|
* MSR_AMD64_BU_CFG2.
|
|
*
|
|
* NOTE: we want to use the _safe accessors so as not to #GP kvm
|
|
* guests on older kvm hosts.
|
|
*/
|
|
|
|
rdmsrl_safe(MSR_AMD64_BU_CFG2, &value);
|
|
value &= ~(1ULL << 24);
|
|
wrmsrl_safe(MSR_AMD64_BU_CFG2, value);
|
|
|
|
if (cpu_has_amd_erratum(c, amd_erratum_383))
|
|
set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
|
|
}
|
|
|
|
if (cpu_has_amd_erratum(c, amd_erratum_400))
|
|
set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
|
|
|
|
rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_32
|
|
static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
|
|
{
|
|
/* AMD errata T13 (order #21922) */
|
|
if ((c->x86 == 6)) {
|
|
/* Duron Rev A0 */
|
|
if (c->x86_model == 3 && c->x86_mask == 0)
|
|
size = 64;
|
|
/* Tbird rev A1/A2 */
|
|
if (c->x86_model == 4 &&
|
|
(c->x86_mask == 0 || c->x86_mask == 1))
|
|
size = 256;
|
|
}
|
|
return size;
|
|
}
|
|
#endif
|
|
|
|
static void cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)
|
|
{
|
|
tlb_flushall_shift = 6;
|
|
}
|
|
|
|
static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
|
|
{
|
|
u32 ebx, eax, ecx, edx;
|
|
u16 mask = 0xfff;
|
|
|
|
if (c->x86 < 0xf)
|
|
return;
|
|
|
|
if (c->extended_cpuid_level < 0x80000006)
|
|
return;
|
|
|
|
cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
|
|
|
|
tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
|
|
tlb_lli_4k[ENTRIES] = ebx & mask;
|
|
|
|
/*
|
|
* K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
|
|
* characteristics from the CPUID function 0x80000005 instead.
|
|
*/
|
|
if (c->x86 == 0xf) {
|
|
cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
|
|
mask = 0xff;
|
|
}
|
|
|
|
/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
|
|
if (!((eax >> 16) & mask))
|
|
tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
|
|
else
|
|
tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
|
|
|
|
/* a 4M entry uses two 2M entries */
|
|
tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
|
|
|
|
/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
|
|
if (!(eax & mask)) {
|
|
/* Erratum 658 */
|
|
if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
|
|
tlb_lli_2m[ENTRIES] = 1024;
|
|
} else {
|
|
cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
|
|
tlb_lli_2m[ENTRIES] = eax & 0xff;
|
|
}
|
|
} else
|
|
tlb_lli_2m[ENTRIES] = eax & mask;
|
|
|
|
tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
|
|
|
|
cpu_set_tlb_flushall_shift(c);
|
|
}
|
|
|
|
static const struct cpu_dev amd_cpu_dev = {
|
|
.c_vendor = "AMD",
|
|
.c_ident = { "AuthenticAMD" },
|
|
#ifdef CONFIG_X86_32
|
|
.legacy_models = {
|
|
{ .family = 4, .model_names =
|
|
{
|
|
[3] = "486 DX/2",
|
|
[7] = "486 DX/2-WB",
|
|
[8] = "486 DX/4",
|
|
[9] = "486 DX/4-WB",
|
|
[14] = "Am5x86-WT",
|
|
[15] = "Am5x86-WB"
|
|
}
|
|
},
|
|
},
|
|
.legacy_cache_size = amd_size_cache,
|
|
#endif
|
|
.c_early_init = early_init_amd,
|
|
.c_detect_tlb = cpu_detect_tlb_amd,
|
|
.c_bsp_init = bsp_init_amd,
|
|
.c_init = init_amd,
|
|
.c_x86_vendor = X86_VENDOR_AMD,
|
|
};
|
|
|
|
cpu_dev_register(amd_cpu_dev);
|
|
|
|
/*
|
|
* AMD errata checking
|
|
*
|
|
* Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
|
|
* AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
|
|
* have an OSVW id assigned, which it takes as first argument. Both take a
|
|
* variable number of family-specific model-stepping ranges created by
|
|
* AMD_MODEL_RANGE().
|
|
*
|
|
* Example:
|
|
*
|
|
* const int amd_erratum_319[] =
|
|
* AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
|
|
* AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
|
|
* AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
|
|
*/
|
|
|
|
#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
|
|
#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
|
|
#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
|
|
((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
|
|
#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
|
|
#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
|
|
#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
|
|
|
|
static const int amd_erratum_400[] =
|
|
AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
|
|
AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
|
|
|
|
static const int amd_erratum_383[] =
|
|
AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
|
|
|
|
|
|
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
|
|
{
|
|
int osvw_id = *erratum++;
|
|
u32 range;
|
|
u32 ms;
|
|
|
|
if (osvw_id >= 0 && osvw_id < 65536 &&
|
|
cpu_has(cpu, X86_FEATURE_OSVW)) {
|
|
u64 osvw_len;
|
|
|
|
rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
|
|
if (osvw_id < osvw_len) {
|
|
u64 osvw_bits;
|
|
|
|
rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
|
|
osvw_bits);
|
|
return osvw_bits & (1ULL << (osvw_id & 0x3f));
|
|
}
|
|
}
|
|
|
|
/* OSVW unavailable or ID unknown, match family-model-stepping range */
|
|
ms = (cpu->x86_model << 4) | cpu->x86_mask;
|
|
while ((range = *erratum++))
|
|
if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
|
|
(ms >= AMD_MODEL_RANGE_START(range)) &&
|
|
(ms <= AMD_MODEL_RANGE_END(range)))
|
|
return true;
|
|
|
|
return false;
|
|
}
|