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94ea9c0521
The following commit:
ddb5cdbafa ("kbuild: generate KSYMTAB entries by modpost")
deprecated <asm/export.h>, which is now a wrapper of <linux/export.h>.
Use <linux/export.h> in *.S as well as in *.c files.
After all the <asm/export.h> lines are replaced, <asm/export.h> and
<asm-generic/export.h> will be removed.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230806145958.380314-2-masahiroy@kernel.org
243 lines
4.9 KiB
ArmAsm
243 lines
4.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2023 Linus Torvalds <torvalds@linux-foundation.org>
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*/
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#include <linux/export.h>
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#include <linux/linkage.h>
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#include <asm/asm.h>
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/*
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* copy_user_nocache - Uncached memory copy with exception handling
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*
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* This copies from user space into kernel space, but the kernel
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* space accesses can take a machine check exception, so they too
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* need exception handling.
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*
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* Note: only 32-bit and 64-bit stores have non-temporal versions,
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* and we only use aligned versions. Any unaligned parts at the
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* start or end of the copy will be done using normal cached stores.
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*
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* Input:
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* rdi destination
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* rsi source
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* edx count
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*
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* Output:
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* rax uncopied bytes or 0 if successful.
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*/
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SYM_FUNC_START(__copy_user_nocache)
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/* If destination is not 7-byte aligned, we'll have to align it */
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testb $7,%dil
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jne .Lalign
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.Lis_aligned:
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cmp $64,%edx
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jb .Lquadwords
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.p2align 4,0x90
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.Lunrolled:
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10: movq (%rsi),%r8
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11: movq 8(%rsi),%r9
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12: movq 16(%rsi),%r10
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13: movq 24(%rsi),%r11
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20: movnti %r8,(%rdi)
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21: movnti %r9,8(%rdi)
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22: movnti %r10,16(%rdi)
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23: movnti %r11,24(%rdi)
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30: movq 32(%rsi),%r8
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31: movq 40(%rsi),%r9
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32: movq 48(%rsi),%r10
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33: movq 56(%rsi),%r11
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40: movnti %r8,32(%rdi)
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41: movnti %r9,40(%rdi)
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42: movnti %r10,48(%rdi)
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43: movnti %r11,56(%rdi)
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addq $64,%rsi
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addq $64,%rdi
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sub $64,%edx
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cmp $64,%edx
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jae .Lunrolled
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/*
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* First set of user mode loads have been done
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* without any stores, so if they fail, we can
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* just try the non-unrolled loop.
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*/
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_ASM_EXTABLE_UA(10b, .Lquadwords)
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_ASM_EXTABLE_UA(11b, .Lquadwords)
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_ASM_EXTABLE_UA(12b, .Lquadwords)
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_ASM_EXTABLE_UA(13b, .Lquadwords)
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/*
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* The second set of user mode loads have been
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* done with 32 bytes stored to the destination,
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* so we need to take that into account before
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* falling back to the unrolled loop.
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*/
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_ASM_EXTABLE_UA(30b, .Lfixup32)
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_ASM_EXTABLE_UA(31b, .Lfixup32)
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_ASM_EXTABLE_UA(32b, .Lfixup32)
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_ASM_EXTABLE_UA(33b, .Lfixup32)
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/*
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* An exception on a write means that we're
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* done, but we need to update the count
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* depending on where in the unrolled loop
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* we were.
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*/
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_ASM_EXTABLE_UA(20b, .Ldone0)
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_ASM_EXTABLE_UA(21b, .Ldone8)
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_ASM_EXTABLE_UA(22b, .Ldone16)
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_ASM_EXTABLE_UA(23b, .Ldone24)
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_ASM_EXTABLE_UA(40b, .Ldone32)
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_ASM_EXTABLE_UA(41b, .Ldone40)
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_ASM_EXTABLE_UA(42b, .Ldone48)
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_ASM_EXTABLE_UA(43b, .Ldone56)
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.Lquadwords:
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cmp $8,%edx
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jb .Llong
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50: movq (%rsi),%rax
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51: movnti %rax,(%rdi)
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addq $8,%rsi
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addq $8,%rdi
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sub $8,%edx
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jmp .Lquadwords
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/*
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* If we fail on the last full quadword, we will
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* not try to do any byte-wise cached accesses.
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* We will try to do one more 4-byte uncached
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* one, though.
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*/
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_ASM_EXTABLE_UA(50b, .Llast4)
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_ASM_EXTABLE_UA(51b, .Ldone0)
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.Llong:
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test $4,%dl
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je .Lword
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60: movl (%rsi),%eax
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61: movnti %eax,(%rdi)
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addq $4,%rsi
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addq $4,%rdi
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sub $4,%edx
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.Lword:
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sfence
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test $2,%dl
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je .Lbyte
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70: movw (%rsi),%ax
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71: movw %ax,(%rdi)
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addq $2,%rsi
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addq $2,%rdi
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sub $2,%edx
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.Lbyte:
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test $1,%dl
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je .Ldone
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80: movb (%rsi),%al
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81: movb %al,(%rdi)
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dec %edx
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.Ldone:
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mov %edx,%eax
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RET
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/*
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* If we fail on the last four bytes, we won't
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* bother with any fixups. It's dead, Jim. Note
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* that there's no need for 'sfence' for any
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* of this, since the exception will have been
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* serializing.
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*/
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_ASM_EXTABLE_UA(60b, .Ldone)
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_ASM_EXTABLE_UA(61b, .Ldone)
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_ASM_EXTABLE_UA(70b, .Ldone)
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_ASM_EXTABLE_UA(71b, .Ldone)
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_ASM_EXTABLE_UA(80b, .Ldone)
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_ASM_EXTABLE_UA(81b, .Ldone)
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/*
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* This is the "head needs aliging" case when
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* the destination isn't 8-byte aligned. The
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* 4-byte case can be done uncached, but any
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* smaller alignment is done with regular stores.
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*/
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.Lalign:
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test $1,%dil
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je .Lalign_word
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test %edx,%edx
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je .Ldone
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90: movb (%rsi),%al
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91: movb %al,(%rdi)
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inc %rsi
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inc %rdi
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dec %edx
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.Lalign_word:
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test $2,%dil
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je .Lalign_long
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cmp $2,%edx
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jb .Lbyte
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92: movw (%rsi),%ax
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93: movw %ax,(%rdi)
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addq $2,%rsi
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addq $2,%rdi
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sub $2,%edx
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.Lalign_long:
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test $4,%dil
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je .Lis_aligned
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cmp $4,%edx
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jb .Lword
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94: movl (%rsi),%eax
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95: movnti %eax,(%rdi)
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addq $4,%rsi
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addq $4,%rdi
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sub $4,%edx
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jmp .Lis_aligned
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/*
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* If we fail on the initial alignment accesses,
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* we're all done. Again, no point in trying to
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* do byte-by-byte probing if the 4-byte load
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* fails - we're not doing any uncached accesses
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* any more.
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*/
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_ASM_EXTABLE_UA(90b, .Ldone)
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_ASM_EXTABLE_UA(91b, .Ldone)
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_ASM_EXTABLE_UA(92b, .Ldone)
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_ASM_EXTABLE_UA(93b, .Ldone)
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_ASM_EXTABLE_UA(94b, .Ldone)
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_ASM_EXTABLE_UA(95b, .Ldone)
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/*
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* Exception table fixups for faults in the middle
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*/
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.Ldone56: sub $8,%edx
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.Ldone48: sub $8,%edx
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.Ldone40: sub $8,%edx
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.Ldone32: sub $8,%edx
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.Ldone24: sub $8,%edx
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.Ldone16: sub $8,%edx
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.Ldone8: sub $8,%edx
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.Ldone0:
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mov %edx,%eax
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RET
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.Lfixup32:
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addq $32,%rsi
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addq $32,%rdi
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sub $32,%edx
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jmp .Lquadwords
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.Llast4:
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52: movl (%rsi),%eax
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53: movnti %eax,(%rdi)
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sfence
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sub $4,%edx
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mov %edx,%eax
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RET
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_ASM_EXTABLE_UA(52b, .Ldone0)
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_ASM_EXTABLE_UA(53b, .Ldone0)
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SYM_FUNC_END(__copy_user_nocache)
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EXPORT_SYMBOL(__copy_user_nocache)
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