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188611af42
This makes it easy to add SMP support for new devices by keying on a device node for the release sequence. We add the enable-method property for the cpus property to specify that we want to use the gcc-msm8660 release sequence (which is going to look for the global clock controller device node to map some Scorpion specific power and control registers). We also remove the nr_cpus detection code as that is done generically in the DT CPU detection code. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> [sboyd: Port to CPU_METHOD_OF_DECLARE] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/smp_plat.h>
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#include "scm-boot.h"
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#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
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#define SCSS_CPU1CORE_RESET 0x2d80
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#define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64
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extern void secondary_startup(void);
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static DEFINE_SPINLOCK(boot_lock);
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#ifdef CONFIG_HOTPLUG_CPU
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static void __ref qcom_cpu_die(unsigned int cpu)
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{
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wfi();
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}
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#endif
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static void qcom_secondary_init(unsigned int cpu)
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{
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int scss_release_secondary(unsigned int cpu)
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{
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struct device_node *node;
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void __iomem *base;
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node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
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if (!node) {
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pr_err("%s: can't find node\n", __func__);
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return -ENXIO;
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}
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base = of_iomap(node, 0);
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of_node_put(node);
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if (!base)
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return -ENOMEM;
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writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
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writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
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writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
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mb();
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iounmap(base);
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return 0;
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}
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static DEFINE_PER_CPU(int, cold_boot_done);
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static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
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{
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int ret = 0;
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if (!per_cpu(cold_boot_done, cpu)) {
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ret = func(cpu);
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if (!ret)
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per_cpu(cold_boot_done, cpu) = true;
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}
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return ret;
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}
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static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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return qcom_boot_secondary(cpu, scss_release_secondary);
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}
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static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
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{
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int cpu, map;
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unsigned int flags = 0;
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static const int cold_boot_flags[] = {
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0,
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SCM_FLAG_COLDBOOT_CPU1,
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};
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for_each_present_cpu(cpu) {
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map = cpu_logical_map(cpu);
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if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
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set_cpu_present(cpu, false);
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continue;
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}
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flags |= cold_boot_flags[map];
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}
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if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) {
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for_each_present_cpu(cpu) {
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if (cpu == smp_processor_id())
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continue;
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set_cpu_present(cpu, false);
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}
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pr_warn("Failed to set CPU boot address, disabling SMP\n");
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}
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}
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static struct smp_operations smp_msm8660_ops __initdata = {
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.smp_prepare_cpus = qcom_smp_prepare_cpus,
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.smp_secondary_init = qcom_secondary_init,
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.smp_boot_secondary = msm8660_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = qcom_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
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