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ARC common code to enable a SMP system + ISS provided SMP extensions. ARC700 natively lacks SMP support, hence some of the core features are are only enabled if SoCs have the necessary h/w pixie-dust. This includes: -Inter Processor Interrupts (IPI) -Cache coherency -load-locked/store-conditional ... The low level exception handling would be completely broken in SMP because we don't have hardware assisted stack switching. Thus a fair bit of this code is repurposing the MMU_SCRATCH reg for event handler prologues to keep them re-entrant. Many thanks to Rajeshwar Ranga for his initial "major" contributions to SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help with resurrecting that in 3.2 kernel (2012). Note that this platform code is again singleton design pattern - so multiple SMP platforms won't build at the moment - this deficiency is addressed in subsequent patches within this series. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rajeshwar Ranga <rajeshwar.ranga@gmail.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Gilad Ben-Yossef <gilad@benyossef.com>
152 lines
4.8 KiB
C
152 lines
4.8 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: March 2009
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* -Implemented task_pt_regs( )
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*
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* Amit Bhor, Sameer Dhavale, Ashwin Chaugule: Codito Technologies 2004
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*/
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#ifndef __ASM_ARC_PROCESSOR_H
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#define __ASM_ARC_PROCESSOR_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/arcregs.h> /* for STATUS_E1_MASK et all */
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/* Arch specific stuff which needs to be saved per task.
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* However these items are not so important so as to earn a place in
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* struct thread_info
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*/
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struct thread_struct {
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unsigned long ksp; /* kernel mode stack pointer */
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unsigned long callee_reg; /* pointer to callee regs */
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unsigned long fault_address; /* dbls as brkpt holder as well */
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unsigned long cause_code; /* Exception Cause Code (ECR) */
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#ifdef CONFIG_ARC_CURR_IN_REG
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unsigned long user_r25;
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#endif
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#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
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struct arc_fpu fpu;
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#endif
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};
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#define INIT_THREAD { \
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.ksp = sizeof(init_stack) + (unsigned long) init_stack, \
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}
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/* Forward declaration, a strange C thing */
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struct task_struct;
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/*
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* Return saved PC of a blocked thread.
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*/
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unsigned long thread_saved_pc(struct task_struct *t);
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#define task_pt_regs(p) \
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((struct pt_regs *)(THREAD_SIZE - 4 + (void *)task_stack_page(p)) - 1)
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/* Free all resources held by a thread. */
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#define release_thread(thread) do { } while (0)
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/* Prepare to copy thread state - unlazy all lazy status */
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#define prepare_to_copy(tsk) do { } while (0)
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/*
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* A lot of busy-wait loops in SMP are based off of non-volatile data otherwise
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* get optimised away by gcc
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*/
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#ifdef CONFIG_SMP
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#define cpu_relax() __asm__ __volatile__ ("" : : : "memory")
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#else
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#define cpu_relax() do { } while (0)
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#endif
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#define copy_segments(tsk, mm) do { } while (0)
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#define release_segments(mm) do { } while (0)
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ret)
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/*
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* Where abouts of Task's sp, fp, blink when it was last seen in kernel mode.
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* These can't be derived from pt_regs as that would give correp user-mode val
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*/
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#define KSTK_ESP(tsk) (tsk->thread.ksp)
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#define KSTK_BLINK(tsk) (*((unsigned int *)((KSTK_ESP(tsk)) + (13+1+1)*4)))
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#define KSTK_FP(tsk) (*((unsigned int *)((KSTK_ESP(tsk)) + (13+1)*4)))
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/*
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* Do necessary setup to start up a newly executed thread.
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*
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* E1,E2 so that Interrupts are enabled in user mode
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* L set, so Loop inhibited to begin with
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* lp_start and lp_end seeded with bogus non-zero values so to easily catch
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* the ARC700 sr to lp_start hardware bug
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*/
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#define start_thread(_regs, _pc, _usp) \
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do { \
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set_fs(USER_DS); /* reads from user space */ \
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(_regs)->ret = (_pc); \
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/* Interrupts enabled in User Mode */ \
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(_regs)->status32 = STATUS_U_MASK | STATUS_L_MASK \
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| STATUS_E1_MASK | STATUS_E2_MASK; \
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(_regs)->sp = (_usp); \
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/* bogus seed values for debugging */ \
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(_regs)->lp_start = 0x10; \
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(_regs)->lp_end = 0x80; \
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} while (0)
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extern unsigned int get_wchan(struct task_struct *p);
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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* Should the PC register be read instead ? This macro does not seem to
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* be used in many places so this wont be all that bad.
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l; })
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#endif /* !__ASSEMBLY__ */
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/* Kernels Virtual memory area.
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* Unlike other architectures(MIPS, sh, cris ) ARC 700 does not have a
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* "kernel translated" region (like KSEG2 in MIPS). So we use a upper part
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* of the translated bottom 2GB for kernel virtual memory and protect
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* these pages from user accesses by disabling Ru, Eu and Wu.
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*/
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#define VMALLOC_SIZE (0x10000000) /* 256M */
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#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
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#define VMALLOC_END (PAGE_OFFSET)
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/* Most of the architectures seem to be keeping some kind of padding between
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* userspace TASK_SIZE and PAGE_OFFSET. i.e TASK_SIZE != PAGE_OFFSET.
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*/
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#define USER_KERNEL_GUTTER 0x10000000
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/* User address space:
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* On ARC700, CPU allows the entire lower half of 32 bit address space to be
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* translated. Thus potentially 2G (0:0x7FFF_FFFF) could be User vaddr space.
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* However we steal 256M for kernel addr (0x7000_0000:0x7FFF_FFFF) and another
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* 256M (0x6000_0000:0x6FFF_FFFF) is gutter between user/kernel spaces
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* Thus total User vaddr space is (0:0x5FFF_FFFF)
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*/
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#define TASK_SIZE (PAGE_OFFSET - VMALLOC_SIZE - USER_KERNEL_GUTTER)
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#define STACK_TOP TASK_SIZE
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#define STACK_TOP_MAX STACK_TOP
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
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#endif /* __KERNEL__ */
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#endif /* __ASM_ARC_PROCESSOR_H */
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