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After moving the the include files there were a few clean-ups: 1) Some files used #include <asm-ia64/xyz.h>, changed to <asm/xyz.h> 2) Some comments alerted maintainers to look at various header files to make matching updates if certain code were to be changed. Updated these comments to use the new include paths. 3) Some header files mentioned their own names in initial comments. Just deleted these self references. Signed-off-by: Tony Luck <tony.luck@intel.com>
162 lines
4.8 KiB
C
162 lines
4.8 KiB
C
#ifndef _ASM_IA64_INTEL_INTRIN_H
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#define _ASM_IA64_INTEL_INTRIN_H
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/*
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* Intel Compiler Intrinsics
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*
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* Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
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* Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
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* Copyright (C) 2005,2006 Hongjiu Lu <hongjiu.lu@intel.com>
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*
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*/
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#include <ia64intrin.h>
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#define ia64_barrier() __memory_barrier()
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#define ia64_stop() /* Nothing: As of now stop bit is generated for each
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* intrinsic
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*/
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#define ia64_native_getreg __getReg
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#define ia64_native_setreg __setReg
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#define ia64_hint __hint
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#define ia64_hint_pause __hint_pause
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#define ia64_mux1_brcst _m64_mux1_brcst
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#define ia64_mux1_mix _m64_mux1_mix
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#define ia64_mux1_shuf _m64_mux1_shuf
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#define ia64_mux1_alt _m64_mux1_alt
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#define ia64_mux1_rev _m64_mux1_rev
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#define ia64_mux1(x,v) _m_to_int64(_m64_mux1(_m_from_int64(x), (v)))
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#define ia64_popcnt _m64_popcnt
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#define ia64_getf_exp __getf_exp
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#define ia64_shrp _m64_shrp
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#define ia64_tpa __tpa
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#define ia64_invala __invala
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#define ia64_invala_gr __invala_gr
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#define ia64_invala_fr __invala_fr
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#define ia64_nop __nop
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#define ia64_sum __sum
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#define ia64_native_ssm __ssm
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#define ia64_rum __rum
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#define ia64_native_rsm __rsm
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#define ia64_native_fc __fc
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#define ia64_ldfs __ldfs
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#define ia64_ldfd __ldfd
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#define ia64_ldfe __ldfe
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#define ia64_ldf8 __ldf8
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#define ia64_ldf_fill __ldf_fill
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#define ia64_stfs __stfs
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#define ia64_stfd __stfd
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#define ia64_stfe __stfe
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#define ia64_stf8 __stf8
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#define ia64_stf_spill __stf_spill
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#define ia64_mf __mf
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#define ia64_mfa __mfa
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#define ia64_fetchadd4_acq __fetchadd4_acq
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#define ia64_fetchadd4_rel __fetchadd4_rel
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#define ia64_fetchadd8_acq __fetchadd8_acq
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#define ia64_fetchadd8_rel __fetchadd8_rel
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#define ia64_xchg1 _InterlockedExchange8
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#define ia64_xchg2 _InterlockedExchange16
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#define ia64_xchg4 _InterlockedExchange
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#define ia64_xchg8 _InterlockedExchange64
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#define ia64_cmpxchg1_rel _InterlockedCompareExchange8_rel
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#define ia64_cmpxchg1_acq _InterlockedCompareExchange8_acq
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#define ia64_cmpxchg2_rel _InterlockedCompareExchange16_rel
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#define ia64_cmpxchg2_acq _InterlockedCompareExchange16_acq
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#define ia64_cmpxchg4_rel _InterlockedCompareExchange_rel
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#define ia64_cmpxchg4_acq _InterlockedCompareExchange_acq
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#define ia64_cmpxchg8_rel _InterlockedCompareExchange64_rel
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#define ia64_cmpxchg8_acq _InterlockedCompareExchange64_acq
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#define __ia64_set_dbr(index, val) \
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__setIndReg(_IA64_REG_INDR_DBR, index, val)
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#define ia64_set_ibr(index, val) \
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__setIndReg(_IA64_REG_INDR_IBR, index, val)
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#define ia64_set_pkr(index, val) \
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__setIndReg(_IA64_REG_INDR_PKR, index, val)
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#define ia64_set_pmc(index, val) \
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__setIndReg(_IA64_REG_INDR_PMC, index, val)
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#define ia64_set_pmd(index, val) \
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__setIndReg(_IA64_REG_INDR_PMD, index, val)
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#define ia64_native_set_rr(index, val) \
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__setIndReg(_IA64_REG_INDR_RR, index, val)
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#define ia64_native_get_cpuid(index) \
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__getIndReg(_IA64_REG_INDR_CPUID, index)
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#define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index)
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#define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index)
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#define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index)
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#define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index)
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#define ia64_native_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index)
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#define ia64_native_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index)
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#define ia64_srlz_d __dsrlz
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#define ia64_srlz_i __isrlz
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#define ia64_dv_serialize_data()
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#define ia64_dv_serialize_instruction()
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#define ia64_st1_rel __st1_rel
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#define ia64_st2_rel __st2_rel
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#define ia64_st4_rel __st4_rel
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#define ia64_st8_rel __st8_rel
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/* FIXME: need st4.rel.nta intrinsic */
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#define ia64_st4_rel_nta __st4_rel
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#define ia64_ld1_acq __ld1_acq
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#define ia64_ld2_acq __ld2_acq
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#define ia64_ld4_acq __ld4_acq
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#define ia64_ld8_acq __ld8_acq
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#define ia64_sync_i __synci
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#define ia64_native_thash __thash
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#define ia64_native_ttag __ttag
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#define ia64_itcd __itcd
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#define ia64_itci __itci
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#define ia64_itrd __itrd
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#define ia64_itri __itri
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#define ia64_ptce __ptce
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#define ia64_ptcl __ptcl
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#define ia64_native_ptcg __ptcg
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#define ia64_native_ptcga __ptcga
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#define ia64_ptri __ptri
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#define ia64_ptrd __ptrd
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#define ia64_dep_mi _m64_dep_mi
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/* Values for lfhint in __lfetch and __lfetch_fault */
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#define ia64_lfhint_none __lfhint_none
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#define ia64_lfhint_nt1 __lfhint_nt1
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#define ia64_lfhint_nt2 __lfhint_nt2
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#define ia64_lfhint_nta __lfhint_nta
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#define ia64_lfetch __lfetch
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#define ia64_lfetch_excl __lfetch_excl
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#define ia64_lfetch_fault __lfetch_fault
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#define ia64_lfetch_fault_excl __lfetch_fault_excl
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#define ia64_native_intrin_local_irq_restore(x) \
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do { \
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if ((x) != 0) { \
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ia64_native_ssm(IA64_PSR_I); \
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ia64_srlz_d(); \
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} else { \
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ia64_native_rsm(IA64_PSR_I); \
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} \
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} while (0)
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#define __builtin_trap() __break(0);
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#endif /* _ASM_IA64_INTEL_INTRIN_H */
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