Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-22 19:01:37 +00:00
Code Issues Packages Projects Releases Wiki Activity
1688bf19b8
linux/arch/arm/mach-omap2/io.c
Linus Torvalds 97e7292ab5 arm-soc: clk changes 
Clock support is moving to the clk subsystem. These tegra, omap and imx
 changes are for code that is still platform specific and not (yet)
 part of that subsystem.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIVAwUAUA2dh2CrR//JCVInAQLm6g//UD7Q6xc/1I9/k0c/V35o4FRgmOt9xIp2
 ofsB801AnYOOusFWkcBa8xb6zFQuNQwR6OflkYBBV+31Zp2cNHgF9SVxaYlh43MD
 iptUnCh8VzSEFFZGy1Vi3sdrKY5fw5dyffPjgv8HtWQzs4r8H+98UnNQFbkTwPft
 9TxAeH73LRm4uNI/E8OerYN78TOefBK8p6HXyNW//MCzb59aG73/iD3EACrAmvyY
 gtyhLMtPeZTUWh3Fy5vXd9cfCmzQOAH/ADeMxVyx2QFyb3vCcPoS8Z5plh3zIjMt
 Ze0KlhHkB5lfBGBOB3gA/7ItlclhL2qLNkuhM2CBgYg+WTZ4OqaJCv80+OK8X4i5
 XCVjuDG++CFH09jDnMPXeUBM6UHwRV3f/HIRhaL8nH+nq1mU5HzEGrvBZTnOIklI
 XNoOpAMVPih64vH8PIQL/8oXT+cNHyVkmKA2uqRKq+mgqC+FIjG7EKBmIVORr7eI
 HmDHtHpRZY9EpK/cfgykDl4ELDITEaaitxvk0uqchSj3SXjfmbBXNKKcInQhDKaZ
 TKRMCgzeTu4NXSrRyHAP2toKUQNSziB7mwL7aHD6LMloqP1jBVOyZpxAIVwt19lZ
 qBAAatYGYocbssypI/E4CptTn3uC3dQiXDHRNJkZC/4o5suZoW9wpT77yvQNR/YQ
 GBO0bhQCI0Y=
 =Cvpa
 -----END PGP SIGNATURE-----

Merge tag 'clk' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc clk changes from Arnd Bergmann:
 "Clock support is moving to the clk subsystem.  These tegra, omap and
  imx changes are for code that is still platform specific and not (yet)
  part of that subsystem."

Fix up conflicts in arch/arm/mach-{imx/clk-imx51-imx53.c,omap2/Makefile}

* tag 'clk' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
  ARM: imx: clk-imx31: Fix clock id for rnga driver
  ARM: imx: add missing item to the list of clock event modes
  ARM: i.MX5x CSPI: Fixed clock name for CSPI
  ARM: i.MX5x clocks: Fix GPT clocks
  ARM: i.MX5x clocks: Fix parent for PWM clocks
  ARM: i.MX5x clocks: Add EPIT support
  ARM: mx27: Reenable silicon version print
  ARM: clk-imx27: Fix rtc clock id
  ARM: tegra: Provide clock for only one PWM controller
  ARM: tegra: Fix PWM clock programming
  ARM: OMAP3+: clock33xx: Add AM33XX clock tree data
  ARM: OMAP3+: clock: Move common clksel_rate & clock data to common file
  ARM: tegra: dma: rename driver name for clock to "tegra-apbdma"
  ARM: tegra: Remove second instance of uart clk
  crypto: add clk_prepare/clk_unprepare
  ASoC: tegra: add clk_prepare/clk_unprepare
  staging: nvec: add clk_prepare/clk_unprepare
  spi/tegra: add clk_prepare/clk_unprepare
  Input: tegra-kbc - add clk_prepare/clk_unprepare
  USB: ehci-tegra: add clk_prepare/clk_unprepare
  ...
2012-07-23 17:51:03 -07:00

572 lines
12 KiB
C
Raw Blame History

/*
* linux/arch/arm/mach-omap2/io.c
*
* OMAP2 I/O mapping code
*
* Copyright (C) 2005 Nokia Corporation
* Copyright (C) 2007-2009 Texas Instruments
*
* Author:
* Juha Yrjola <juha.yrjola@nokia.com>
* Syed Khasim <x0khasim@ti.com>
*
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/tlb.h>
#include <asm/mach/map.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include <plat/serial.h>
#include <plat/omap-pm.h>
#include <plat/omap_hwmod.h>
#include <plat/multi.h>
#include <plat/dma.h>
#include "iomap.h"
#include "voltage.h"
#include "powerdomain.h"
#include "clockdomain.h"
#include "common.h"
#include "clock.h"
#include "clock2xxx.h"
#include "clock3xxx.h"
#include "clock44xx.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
static struct map_desc omap24xx_io_desc[] __initdata = {
{
.virtual = L3_24XX_VIRT,
.pfn = __phys_to_pfn(L3_24XX_PHYS),
.length = L3_24XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_24XX_VIRT,
.pfn = __phys_to_pfn(L4_24XX_PHYS),
.length = L4_24XX_SIZE,
.type = MT_DEVICE
},
};
#ifdef CONFIG_SOC_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
{
.virtual = DSP_MEM_2420_VIRT,
.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
.length = DSP_MEM_2420_SIZE,
.type = MT_DEVICE
},
{
.virtual = DSP_IPI_2420_VIRT,
.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
.length = DSP_IPI_2420_SIZE,
.type = MT_DEVICE
},
{
.virtual = DSP_MMU_2420_VIRT,
.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
.length = DSP_MMU_2420_SIZE,
.type = MT_DEVICE
},
};
#endif
#ifdef CONFIG_SOC_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
{
.virtual = L4_WK_243X_VIRT,
.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
.length = L4_WK_243X_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP243X_GPMC_VIRT,
.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
.length = OMAP243X_GPMC_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP243X_SDRC_VIRT,
.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
.length = OMAP243X_SDRC_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP243X_SMS_VIRT,
.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
.length = OMAP243X_SMS_SIZE,
.type = MT_DEVICE
},
};
#endif
#endif
#ifdef CONFIG_ARCH_OMAP3
static struct map_desc omap34xx_io_desc[] __initdata = {
{
.virtual = L3_34XX_VIRT,
.pfn = __phys_to_pfn(L3_34XX_PHYS),
.length = L3_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP34XX_GPMC_VIRT,
.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
.length = OMAP34XX_GPMC_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP343X_SMS_VIRT,
.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
.length = OMAP343X_SMS_SIZE,
.type = MT_DEVICE
},
{
.virtual = OMAP343X_SDRC_VIRT,
.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
.length = OMAP343X_SDRC_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_PER_34XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
.length = L4_PER_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_EMU_34XX_VIRT,
.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
.length = L4_EMU_34XX_SIZE,
.type = MT_DEVICE
},
#if defined(CONFIG_DEBUG_LL) && \
(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
{
.virtual = ZOOM_UART_VIRT,
.pfn = __phys_to_pfn(ZOOM_UART_BASE),
.length = SZ_1M,
.type = MT_DEVICE
},
#endif
};
#endif
#ifdef CONFIG_SOC_TI81XX
static struct map_desc omapti81xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
}
};
#endif
#ifdef CONFIG_SOC_AM33XX
static struct map_desc omapam33xx_io_desc[] __initdata = {
{
.virtual = L4_34XX_VIRT,
.pfn = __phys_to_pfn(L4_34XX_PHYS),
.length = L4_34XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_WK_AM33XX_VIRT,
.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
.length = L4_WK_AM33XX_SIZE,
.type = MT_DEVICE
}
};
#endif
#ifdef CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
{
.virtual = L3_44XX_VIRT,
.pfn = __phys_to_pfn(L3_44XX_PHYS),
.length = L3_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_44XX_VIRT,
.pfn = __phys_to_pfn(L4_44XX_PHYS),
.length = L4_44XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER_44XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
.length = L4_PER_44XX_SIZE,
.type = MT_DEVICE,
},
#ifdef CONFIG_OMAP4_ERRATA_I688
{
.virtual = OMAP4_SRAM_VA,
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
.length = PAGE_SIZE,
.type = MT_MEMORY_SO,
},
#endif
};
#endif
#ifdef CONFIG_SOC_OMAP5
static struct map_desc omap54xx_io_desc[] __initdata = {
{
.virtual = L3_54XX_VIRT,
.pfn = __phys_to_pfn(L3_54XX_PHYS),
.length = L3_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_54XX_VIRT,
.pfn = __phys_to_pfn(L4_54XX_PHYS),
.length = L4_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_WK_54XX_VIRT,
.pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
.length = L4_WK_54XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER_54XX_VIRT,
.pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
.length = L4_PER_54XX_SIZE,
.type = MT_DEVICE,
},
};
#endif
#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_common_io(void)
{
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
}
#endif
#ifdef CONFIG_SOC_OMAP2430
void __init omap243x_map_common_io(void)
{
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
}
#endif
#ifdef CONFIG_ARCH_OMAP3
void __init omap34xx_map_common_io(void)
{
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
}
#endif
#ifdef CONFIG_SOC_TI81XX
void __init omapti81xx_map_common_io(void)
{
iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
}
#endif
#ifdef CONFIG_SOC_AM33XX
void __init omapam33xx_map_common_io(void)
{
iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
}
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap44xx_map_common_io(void)
{
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
omap_barriers_init();
}
#endif
#ifdef CONFIG_SOC_OMAP5
void __init omap5_map_common_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
}
#endif
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
* Sets the CORE DPLL3 M2 divider to the same value that it's at
* currently. This has the effect of setting the SDRC SDRAM AC timing
* registers to the values currently defined by the kernel. Currently
* only defined for OMAP3; will return 0 if called on OMAP2. Returns
* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
* or passes along the return value of clk_set_rate().
*/
static int __init _omap2_init_reprogram_sdrc(void)
{
struct clk *dpll3_m2_ck;
int v = -EINVAL;
long rate;
if (!cpu_is_omap34xx())
return 0;
dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
if (IS_ERR(dpll3_m2_ck))
return -EINVAL;
rate = clk_get_rate(dpll3_m2_ck);
pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
v = clk_set_rate(dpll3_m2_ck, rate);
if (v)
pr_err("dpll3_m2_clk rate change failed: %d\n", v);
clk_put(dpll3_m2_ck);
return v;
}
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
{
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}
static void __init omap_common_init_early(void)
{
omap_init_consistent_dma_size();
}
static void __init omap_hwmod_init_postsetup(void)
{
u8 postsetup_state;
/* Set the default postsetup state for all hwmods */
#ifdef CONFIG_PM_RUNTIME
postsetup_state = _HWMOD_STATE_IDLE;
#else
postsetup_state = _HWMOD_STATE_ENABLED;
#endif
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
omap_pm_if_early_init();
}
#ifdef CONFIG_SOC_OMAP2420
void __init omap2420_init_early(void)
{
omap2_set_globals_242x();
omap2xxx_check_revision();
omap_common_init_early();
omap2xxx_voltagedomains_init();
omap242x_powerdomains_init();
omap242x_clockdomains_init();
omap2420_hwmod_init();
omap_hwmod_init_postsetup();
omap2420_clk_init();
}
void __init omap2420_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap2_pm_init();
}
#endif
#ifdef CONFIG_SOC_OMAP2430
void __init omap2430_init_early(void)
{
omap2_set_globals_243x();
omap2xxx_check_revision();
omap_common_init_early();
omap2xxx_voltagedomains_init();
omap243x_powerdomains_init();
omap243x_clockdomains_init();
omap2430_hwmod_init();
omap_hwmod_init_postsetup();
omap2430_clk_init();
}
void __init omap2430_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap2_pm_init();
}
#endif
/*
* Currently only board-omap3beagle.c should call this because of the
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
*/
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_init_early(void)
{
omap2_set_globals_3xxx();
omap3xxx_check_revision();
omap3xxx_check_features();
omap_common_init_early();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
omap3xxx_clk_init();
}
void __init omap3430_init_early(void)
{
omap3_init_early();
}
void __init omap35xx_init_early(void)
{
omap3_init_early();
}
void __init omap3630_init_early(void)
{
omap3_init_early();
}
void __init am35xx_init_early(void)
{
omap3_init_early();
}
void __init ti81xx_init_early(void)
{
omap2_set_globals_ti81xx();
omap3xxx_check_revision();
ti81xx_check_features();
omap_common_init_early();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
omap3xxx_clk_init();
}
void __init omap3_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap3_pm_init();
}
void __init omap3430_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap3_pm_init();
}
void __init omap35xx_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap3_pm_init();
}
void __init omap3630_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap3_pm_init();
}
void __init am35xx_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap3_pm_init();
}
void __init ti81xx_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap3_pm_init();
}
#endif
#ifdef CONFIG_SOC_AM33XX
void __init am33xx_init_early(void)
{
omap2_set_globals_am33xx();
omap3xxx_check_revision();
ti81xx_check_features();
omap_common_init_early();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
am33xx_clk_init();
}
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap4430_init_early(void)
{
omap2_set_globals_443x();
omap4xxx_check_revision();
omap4xxx_check_features();
omap_common_init_early();
omap44xx_voltagedomains_init();
omap44xx_powerdomains_init();
omap44xx_clockdomains_init();
omap44xx_hwmod_init();
omap_hwmod_init_postsetup();
omap4xxx_clk_init();
}
void __init omap4430_init_late(void)
{
omap_mux_late_init();
omap2_common_pm_late_init();
omap4_pm_init();
}
#endif
#ifdef CONFIG_SOC_OMAP5
void __init omap5_init_early(void)
{
omap2_set_globals_5xxx();
omap5xxx_check_revision();
omap_common_init_early();
}
#endif
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
omap_sram_init();
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
}
Reference in New Issue View Git Blame Copy Permalink