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32aaeffbd4
* 'modsplit-Oct31_2011' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux: (230 commits) Revert "tracing: Include module.h in define_trace.h" irq: don't put module.h into irq.h for tracking irqgen modules. bluetooth: macroize two small inlines to avoid module.h ip_vs.h: fix implicit use of module_get/module_put from module.h nf_conntrack.h: fix up fallout from implicit moduleparam.h presence include: replace linux/module.h with "struct module" wherever possible include: convert various register fcns to macros to avoid include chaining crypto.h: remove unused crypto_tfm_alg_modname() inline uwb.h: fix implicit use of asm/page.h for PAGE_SIZE pm_runtime.h: explicitly requires notifier.h linux/dmaengine.h: fix implicit use of bitmap.h and asm/page.h miscdevice.h: fix up implicit use of lists and types stop_machine.h: fix implicit use of smp.h for smp_processor_id of: fix implicit use of errno.h in include/linux/of.h of_platform.h: delete needless include <linux/module.h> acpi: remove module.h include from platform/aclinux.h miscdevice.h: delete unnecessary inclusion of module.h device_cgroup.h: delete needless include <linux/module.h> net: sch_generic remove redundant use of <linux/module.h> net: inet_timewait_sock doesnt need <linux/module.h> ... Fix up trivial conflicts (other header files, and removal of the ab3550 mfd driver) in - drivers/media/dvb/frontends/dibx000_common.c - drivers/media/video/{mt9m111.c,ov6650.c} - drivers/mfd/ab3550-core.c - include/linux/dmaengine.h
446 lines
11 KiB
C
446 lines
11 KiB
C
/*
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* drivers/dma/imx-dma.c
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*
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* This file contains a driver for the Freescale i.MX DMA engine
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* found on i.MX1/21/27
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*
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* Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <asm/irq.h>
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#include <mach/dma-v1.h>
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#include <mach/hardware.h>
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struct imxdma_channel {
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struct imxdma_engine *imxdma;
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unsigned int channel;
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unsigned int imxdma_channel;
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enum dma_slave_buswidth word_size;
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dma_addr_t per_address;
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u32 watermark_level;
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struct dma_chan chan;
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spinlock_t lock;
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struct dma_async_tx_descriptor desc;
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dma_cookie_t last_completed;
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enum dma_status status;
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int dma_request;
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struct scatterlist *sg_list;
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};
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#define MAX_DMA_CHANNELS 8
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struct imxdma_engine {
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struct device *dev;
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struct device_dma_parameters dma_parms;
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struct dma_device dma_device;
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struct imxdma_channel channel[MAX_DMA_CHANNELS];
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};
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static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct imxdma_channel, chan);
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}
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static void imxdma_handle(struct imxdma_channel *imxdmac)
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{
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if (imxdmac->desc.callback)
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imxdmac->desc.callback(imxdmac->desc.callback_param);
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imxdmac->last_completed = imxdmac->desc.cookie;
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}
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static void imxdma_irq_handler(int channel, void *data)
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{
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struct imxdma_channel *imxdmac = data;
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imxdmac->status = DMA_SUCCESS;
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imxdma_handle(imxdmac);
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}
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static void imxdma_err_handler(int channel, void *data, int error)
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{
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struct imxdma_channel *imxdmac = data;
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imxdmac->status = DMA_ERROR;
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imxdma_handle(imxdmac);
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}
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static void imxdma_progression(int channel, void *data,
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struct scatterlist *sg)
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{
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struct imxdma_channel *imxdmac = data;
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imxdmac->status = DMA_SUCCESS;
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imxdma_handle(imxdmac);
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}
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static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct dma_slave_config *dmaengine_cfg = (void *)arg;
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int ret;
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unsigned int mode = 0;
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switch (cmd) {
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case DMA_TERMINATE_ALL:
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imxdmac->status = DMA_ERROR;
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imx_dma_disable(imxdmac->imxdma_channel);
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return 0;
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case DMA_SLAVE_CONFIG:
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if (dmaengine_cfg->direction == DMA_FROM_DEVICE) {
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imxdmac->per_address = dmaengine_cfg->src_addr;
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imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
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imxdmac->word_size = dmaengine_cfg->src_addr_width;
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} else {
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imxdmac->per_address = dmaengine_cfg->dst_addr;
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imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
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imxdmac->word_size = dmaengine_cfg->dst_addr_width;
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}
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switch (imxdmac->word_size) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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mode = IMX_DMA_MEMSIZE_8;
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break;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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mode = IMX_DMA_MEMSIZE_16;
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break;
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default:
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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mode = IMX_DMA_MEMSIZE_32;
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break;
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}
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ret = imx_dma_config_channel(imxdmac->imxdma_channel,
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mode | IMX_DMA_TYPE_FIFO,
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IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
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imxdmac->dma_request, 1);
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if (ret)
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return ret;
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imx_dma_config_burstlen(imxdmac->imxdma_channel,
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imxdmac->watermark_level * imxdmac->word_size);
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return 0;
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default:
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return -ENOSYS;
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}
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return -EINVAL;
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}
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static enum dma_status imxdma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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dma_cookie_t last_used;
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enum dma_status ret;
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last_used = chan->cookie;
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ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
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dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
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return ret;
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}
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static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
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{
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dma_cookie_t cookie = imxdma->chan.cookie;
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if (++cookie < 0)
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cookie = 1;
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imxdma->chan.cookie = cookie;
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imxdma->desc.cookie = cookie;
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return cookie;
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}
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static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
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dma_cookie_t cookie;
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spin_lock_irq(&imxdmac->lock);
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cookie = imxdma_assign_cookie(imxdmac);
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imx_dma_enable(imxdmac->imxdma_channel);
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spin_unlock_irq(&imxdmac->lock);
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return cookie;
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}
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static int imxdma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct imx_dma_data *data = chan->private;
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imxdmac->dma_request = data->dma_request;
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dma_async_tx_descriptor_init(&imxdmac->desc, chan);
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imxdmac->desc.tx_submit = imxdma_tx_submit;
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/* txd.flags will be overwritten in prep funcs */
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imxdmac->desc.flags = DMA_CTRL_ACK;
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imxdmac->status = DMA_SUCCESS;
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return 0;
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}
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static void imxdma_free_chan_resources(struct dma_chan *chan)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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imx_dma_disable(imxdmac->imxdma_channel);
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if (imxdmac->sg_list) {
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kfree(imxdmac->sg_list);
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imxdmac->sg_list = NULL;
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}
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}
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static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_data_direction direction,
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unsigned long flags)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct scatterlist *sg;
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int i, ret, dma_length = 0;
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unsigned int dmamode;
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if (imxdmac->status == DMA_IN_PROGRESS)
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return NULL;
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imxdmac->status = DMA_IN_PROGRESS;
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for_each_sg(sgl, sg, sg_len, i) {
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dma_length += sg->length;
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}
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if (direction == DMA_FROM_DEVICE)
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dmamode = DMA_MODE_READ;
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else
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dmamode = DMA_MODE_WRITE;
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switch (imxdmac->word_size) {
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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if (sgl->length & 3 || sgl->dma_address & 3)
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return NULL;
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break;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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if (sgl->length & 1 || sgl->dma_address & 1)
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return NULL;
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break;
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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break;
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default:
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return NULL;
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}
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ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
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dma_length, imxdmac->per_address, dmamode);
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if (ret)
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return NULL;
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return &imxdmac->desc;
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}
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static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
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size_t period_len, enum dma_data_direction direction)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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int i, ret;
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unsigned int periods = buf_len / period_len;
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unsigned int dmamode;
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dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
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__func__, imxdmac->channel, buf_len, period_len);
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if (imxdmac->status == DMA_IN_PROGRESS)
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return NULL;
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imxdmac->status = DMA_IN_PROGRESS;
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ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
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imxdma_progression);
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if (ret) {
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dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
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return NULL;
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}
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if (imxdmac->sg_list)
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kfree(imxdmac->sg_list);
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imxdmac->sg_list = kcalloc(periods + 1,
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sizeof(struct scatterlist), GFP_KERNEL);
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if (!imxdmac->sg_list)
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return NULL;
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sg_init_table(imxdmac->sg_list, periods);
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for (i = 0; i < periods; i++) {
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imxdmac->sg_list[i].page_link = 0;
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imxdmac->sg_list[i].offset = 0;
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imxdmac->sg_list[i].dma_address = dma_addr;
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imxdmac->sg_list[i].length = period_len;
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dma_addr += period_len;
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}
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/* close the loop */
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imxdmac->sg_list[periods].offset = 0;
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imxdmac->sg_list[periods].length = 0;
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imxdmac->sg_list[periods].page_link =
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((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
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if (direction == DMA_FROM_DEVICE)
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dmamode = DMA_MODE_READ;
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else
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dmamode = DMA_MODE_WRITE;
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ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
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IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
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if (ret)
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return NULL;
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return &imxdmac->desc;
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}
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static void imxdma_issue_pending(struct dma_chan *chan)
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{
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/*
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* Nothing to do. We only have a single descriptor
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*/
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}
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static int __init imxdma_probe(struct platform_device *pdev)
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{
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struct imxdma_engine *imxdma;
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int ret, i;
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imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
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if (!imxdma)
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return -ENOMEM;
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INIT_LIST_HEAD(&imxdma->dma_device.channels);
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dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
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dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
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/* Initialize channel parameters */
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for (i = 0; i < MAX_DMA_CHANNELS; i++) {
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struct imxdma_channel *imxdmac = &imxdma->channel[i];
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imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
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DMA_PRIO_MEDIUM);
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if ((int)imxdmac->channel < 0) {
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ret = -ENODEV;
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goto err_init;
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}
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imx_dma_setup_handlers(imxdmac->imxdma_channel,
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imxdma_irq_handler, imxdma_err_handler, imxdmac);
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imxdmac->imxdma = imxdma;
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spin_lock_init(&imxdmac->lock);
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imxdmac->chan.device = &imxdma->dma_device;
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imxdmac->channel = i;
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/* Add the channel to the DMAC list */
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list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
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}
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imxdma->dev = &pdev->dev;
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imxdma->dma_device.dev = &pdev->dev;
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imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
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imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
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imxdma->dma_device.device_tx_status = imxdma_tx_status;
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imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
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imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
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imxdma->dma_device.device_control = imxdma_control;
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imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
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platform_set_drvdata(pdev, imxdma);
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imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
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dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
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ret = dma_async_device_register(&imxdma->dma_device);
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if (ret) {
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dev_err(&pdev->dev, "unable to register\n");
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goto err_init;
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}
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return 0;
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err_init:
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while (--i >= 0) {
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struct imxdma_channel *imxdmac = &imxdma->channel[i];
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imx_dma_free(imxdmac->imxdma_channel);
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}
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kfree(imxdma);
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return ret;
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}
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static int __exit imxdma_remove(struct platform_device *pdev)
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{
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struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
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int i;
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dma_async_device_unregister(&imxdma->dma_device);
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for (i = 0; i < MAX_DMA_CHANNELS; i++) {
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struct imxdma_channel *imxdmac = &imxdma->channel[i];
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imx_dma_free(imxdmac->imxdma_channel);
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}
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kfree(imxdma);
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return 0;
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}
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static struct platform_driver imxdma_driver = {
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.driver = {
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.name = "imx-dma",
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},
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.remove = __exit_p(imxdma_remove),
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};
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static int __init imxdma_module_init(void)
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{
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return platform_driver_probe(&imxdma_driver, imxdma_probe);
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}
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subsys_initcall(imxdma_module_init);
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MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
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MODULE_DESCRIPTION("i.MX dma driver");
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MODULE_LICENSE("GPL");
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