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Document the RZ/G2E (a.k.a. r8a774c0) SoC in the R-Car DU bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
121 lines
4.9 KiB
Plaintext
121 lines
4.9 KiB
Plaintext
* Renesas R-Car Display Unit (DU)
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Required Properties:
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- compatible: must be one of the following.
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- "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
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- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
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- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
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- "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
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- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
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- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
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- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
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- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
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- "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
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- "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
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- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
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- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
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- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
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- "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
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- "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
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- "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU
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- "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU
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- "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
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- reg: the memory-mapped I/O registers base address and length
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- interrupts: Interrupt specifiers for the DU interrupts.
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- clocks: A list of phandles + clock-specifier pairs, one for each entry in
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the clock-names property.
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- clock-names: Name of the clocks. This property is model-dependent.
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- R8A7779 uses a single functional clock. The clock doesn't need to be
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named.
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- All other DU instances use one functional clock per channel The
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functional clocks must be named "du.x" with "x" being the channel
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numerical index.
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- In addition to the functional clocks, all DU versions also support
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externally supplied pixel clocks. Those clocks are optional. When
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supplied they must be named "dclkin.x" with "x" being the input clock
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numerical index.
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- vsps: A list of phandle and channel index tuples to the VSPs that handle
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the memory interfaces for the DU channels. The phandle identifies the VSP
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instance that serves the DU channel, and the channel index identifies the
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LIF instance in that VSP.
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Required nodes:
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The connections to the DU output video ports are modeled using the OF graph
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bindings specified in Documentation/devicetree/bindings/graph.txt.
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The following table lists for each supported model the port number
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corresponding to each DU output.
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Port0 Port1 Port2 Port3
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-----------------------------------------------------------------------------
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R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
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R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
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R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
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R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
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R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
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R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
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R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
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R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
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R8A7792 (R-Car V2H) DPAD 0 DPAD 1 - -
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R8A7793 (R-Car M2-N) DPAD 0 LVDS 0 - -
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R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
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R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
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R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
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R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
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R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
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R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - -
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R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 -
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R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
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Example: R8A7795 (R-Car H3) ES2.0 DU
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du: display@feb00000 {
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compatible = "renesas,du-r8a7795";
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reg = <0 0xfeb00000 0 0x80000>;
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>,
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<&cpg CPG_MOD 721>;
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clock-names = "du.0", "du.1", "du.2", "du.3";
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vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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du_out_rgb: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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du_out_hdmi0: endpoint {
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remote-endpoint = <&dw_hdmi0_in>;
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};
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};
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port@2 {
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reg = <2>;
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du_out_hdmi1: endpoint {
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remote-endpoint = <&dw_hdmi1_in>;
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};
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};
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port@3 {
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reg = <3>;
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du_out_lvds0: endpoint {
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};
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};
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};
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};
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