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The first variants of Armada XP SoCs (A0 stepping) have issues related to the i2c controller which prevent to use the offload mechanism and lead to a kernel hang during boot. The commit introduces a new the compatible string marvell,mv78230-a0-i2c for the i2c controller. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> cc: devicetree@vger.kernel.org Cc: stable@vger.kernel.org # v3.12+:af8d1c63af: ARM: mvebu: Add support to get the ID and the revision of a SoC Cc: stable@vger.kernel.org # v3.12+:85e618a1be: ARM: mvebu: Add quirk for i2c for the OpenBlocks AX3-4 board Cc: stable@vger.kernel.org # v3.12+:6cf70ae928: i2c: mv64xxx: Fix bus hang on A0 version of the Armada XP SoCs Cc: stable@vger.kernel.org # v3.12+ Fixes:930ab3d403(i2c: mv64xxx: Add I2C Transaction Generator support) Signed-off-by: Jason Cooper <jason@lakedaemon.net>
37 lines
1.0 KiB
Plaintext
37 lines
1.0 KiB
Plaintext
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* Marvell MV64XXX I2C controller
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Required properties :
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- reg : Offset and length of the register set for the device
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- compatible : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c"
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or "marvell,mv78230-i2c" or "marvell,mv78230-a0-i2c"
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Note: Only use "marvell,mv78230-a0-i2c" for a very rare,
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initial version of the SoC which had broken offload
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support. Linux auto-detects this and sets it
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appropriately.
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- interrupts : The interrupt number
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Optional properties :
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- clock-frequency : Desired I2C bus clock frequency in Hz. If not set the
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default frequency is 100kHz
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Examples:
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i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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interrupts = <29>;
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clock-frequency = <100000>;
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};
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For the Armada XP:
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i2c@11000 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x100>;
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interrupts = <29>;
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clock-frequency = <100000>;
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};
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