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929c972e95
Z7 and Z9 have the same PCI ID, so additional checking is needed to detect Z9. The method was "documented" in XGI's xgifb driver. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Thomas Winischhofer <thomas@winischhofer.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
587 lines
16 KiB
C
587 lines
16 KiB
C
/*
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* SiS 300/540/630[S]/730[S],
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* SiS 315[E|PRO]/550/[M]65x/[M]661[F|M]X/740/[M]741[GX]/330/[M]76x[GX],
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* XGI V3XT/V5/V8, Z7
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* frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3
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*
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* Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the named License,
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* or any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifndef _SIS_H_
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#define _SIS_H_
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#include <video/sisfb.h>
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#include "vgatypes.h"
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#include "vstruct.h"
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#define VER_MAJOR 1
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#define VER_MINOR 8
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#define VER_LEVEL 9
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#include <linux/spinlock.h>
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#ifdef CONFIG_COMPAT
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#define SIS_NEW_CONFIG_COMPAT
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#endif /* CONFIG_COMPAT */
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#undef SISFBDEBUG
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#ifdef SISFBDEBUG
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#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
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#define TWDEBUG(x) printk(KERN_INFO x "\n");
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#else
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#define DPRINTK(fmt, args...)
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#define TWDEBUG(x)
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#endif
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#define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)
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/* To be included in pci_ids.h */
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#ifndef PCI_DEVICE_ID_SI_650_VGA
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#define PCI_DEVICE_ID_SI_650_VGA 0x6325
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#endif
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#ifndef PCI_DEVICE_ID_SI_650
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#define PCI_DEVICE_ID_SI_650 0x0650
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#endif
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#ifndef PCI_DEVICE_ID_SI_651
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#define PCI_DEVICE_ID_SI_651 0x0651
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#endif
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#ifndef PCI_DEVICE_ID_SI_740
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#define PCI_DEVICE_ID_SI_740 0x0740
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#endif
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#ifndef PCI_DEVICE_ID_SI_330
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#define PCI_DEVICE_ID_SI_330 0x0330
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#endif
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#ifndef PCI_DEVICE_ID_SI_660_VGA
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#define PCI_DEVICE_ID_SI_660_VGA 0x6330
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#endif
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#ifndef PCI_DEVICE_ID_SI_661
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#define PCI_DEVICE_ID_SI_661 0x0661
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#endif
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#ifndef PCI_DEVICE_ID_SI_741
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#define PCI_DEVICE_ID_SI_741 0x0741
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#endif
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#ifndef PCI_DEVICE_ID_SI_660
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#define PCI_DEVICE_ID_SI_660 0x0660
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#endif
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#ifndef PCI_DEVICE_ID_SI_760
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#define PCI_DEVICE_ID_SI_760 0x0760
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#endif
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#ifndef PCI_DEVICE_ID_SI_761
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#define PCI_DEVICE_ID_SI_761 0x0761
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#endif
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#ifndef PCI_VENDOR_ID_XGI
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#define PCI_VENDOR_ID_XGI 0x18ca
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#endif
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#ifndef PCI_DEVICE_ID_XGI_20
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#define PCI_DEVICE_ID_XGI_20 0x0020
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#endif
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#ifndef PCI_DEVICE_ID_XGI_40
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#define PCI_DEVICE_ID_XGI_40 0x0040
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#endif
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/* To be included in fb.h */
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#ifndef FB_ACCEL_SIS_GLAMOUR_2
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#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 65x, 740, 661, 741 */
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#endif
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#ifndef FB_ACCEL_SIS_XABRE
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#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre"), 76x */
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#endif
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#ifndef FB_ACCEL_XGI_VOLARI_V
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#define FB_ACCEL_XGI_VOLARI_V 47 /* XGI Volari Vx (V3XT, V5, V8) */
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#endif
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#ifndef FB_ACCEL_XGI_VOLARI_Z
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#define FB_ACCEL_XGI_VOLARI_Z 48 /* XGI Volari Z7 */
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#endif
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/* ivideo->caps */
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#define HW_CURSOR_CAP 0x80
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#define TURBO_QUEUE_CAP 0x40
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#define AGP_CMD_QUEUE_CAP 0x20
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#define VM_CMD_QUEUE_CAP 0x10
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#define MMIO_CMD_QUEUE_CAP 0x08
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/* For 300 series */
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#define TURBO_QUEUE_AREA_SIZE (512 * 1024) /* 512K */
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#define HW_CURSOR_AREA_SIZE_300 4096 /* 4K */
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/* For 315/Xabre series */
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#define COMMAND_QUEUE_AREA_SIZE (512 * 1024) /* 512K */
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#define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024) /* 128k for XGI Z7 */
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#define HW_CURSOR_AREA_SIZE_315 16384 /* 16K */
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#define COMMAND_QUEUE_THRESHOLD 0x1F
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#define SIS_OH_ALLOC_SIZE 4000
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#define SENTINEL 0x7fffffff
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#define SEQ_ADR 0x14
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#define SEQ_DATA 0x15
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#define DAC_ADR 0x18
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#define DAC_DATA 0x19
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#define CRTC_ADR 0x24
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#define CRTC_DATA 0x25
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#define DAC2_ADR (0x16-0x30)
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#define DAC2_DATA (0x17-0x30)
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#define VB_PART1_ADR (0x04-0x30)
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#define VB_PART1_DATA (0x05-0x30)
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#define VB_PART2_ADR (0x10-0x30)
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#define VB_PART2_DATA (0x11-0x30)
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#define VB_PART3_ADR (0x12-0x30)
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#define VB_PART3_DATA (0x13-0x30)
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#define VB_PART4_ADR (0x14-0x30)
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#define VB_PART4_DATA (0x15-0x30)
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#define SISSR ivideo->SiS_Pr.SiS_P3c4
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#define SISCR ivideo->SiS_Pr.SiS_P3d4
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#define SISDACA ivideo->SiS_Pr.SiS_P3c8
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#define SISDACD ivideo->SiS_Pr.SiS_P3c9
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#define SISPART1 ivideo->SiS_Pr.SiS_Part1Port
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#define SISPART2 ivideo->SiS_Pr.SiS_Part2Port
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#define SISPART3 ivideo->SiS_Pr.SiS_Part3Port
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#define SISPART4 ivideo->SiS_Pr.SiS_Part4Port
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#define SISPART5 ivideo->SiS_Pr.SiS_Part5Port
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#define SISDAC2A SISPART5
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#define SISDAC2D (SISPART5 + 1)
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#define SISMISCR (ivideo->SiS_Pr.RelIO + 0x1c)
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#define SISMISCW ivideo->SiS_Pr.SiS_P3c2
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#define SISINPSTAT (ivideo->SiS_Pr.RelIO + 0x2a)
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#define SISPEL ivideo->SiS_Pr.SiS_P3c6
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#define SISVGAENABLE (ivideo->SiS_Pr.RelIO + 0x13)
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#define SISVID (ivideo->SiS_Pr.RelIO + 0x02 - 0x30)
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#define SISCAP (ivideo->SiS_Pr.RelIO + 0x00 - 0x30)
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#define IND_SIS_PASSWORD 0x05 /* SRs */
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#define IND_SIS_COLOR_MODE 0x06
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#define IND_SIS_RAMDAC_CONTROL 0x07
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#define IND_SIS_DRAM_SIZE 0x14
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#define IND_SIS_MODULE_ENABLE 0x1E
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#define IND_SIS_PCI_ADDRESS_SET 0x20
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#define IND_SIS_TURBOQUEUE_ADR 0x26
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#define IND_SIS_TURBOQUEUE_SET 0x27
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#define IND_SIS_POWER_ON_TRAP 0x38
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#define IND_SIS_POWER_ON_TRAP2 0x39
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#define IND_SIS_CMDQUEUE_SET 0x26
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#define IND_SIS_CMDQUEUE_THRESHOLD 0x27
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#define IND_SIS_AGP_IO_PAD 0x48
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#define SIS_CRT2_WENABLE_300 0x24 /* Part1 */
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#define SIS_CRT2_WENABLE_315 0x2F
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#define SIS_PASSWORD 0x86 /* SR05 */
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#define SIS_INTERLACED_MODE 0x20 /* SR06 */
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#define SIS_8BPP_COLOR_MODE 0x0
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#define SIS_15BPP_COLOR_MODE 0x1
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#define SIS_16BPP_COLOR_MODE 0x2
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#define SIS_32BPP_COLOR_MODE 0x4
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#define SIS_ENABLE_2D 0x40 /* SR1E */
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#define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */
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#define SIS_PCI_ADDR_ENABLE 0x80
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#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/330/340 series SR26 */
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#define SIS_VRAM_CMDQUEUE_ENABLE 0x40
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#define SIS_MMIO_CMD_ENABLE 0x20
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#define SIS_CMD_QUEUE_SIZE_512k 0x00
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#define SIS_CMD_QUEUE_SIZE_1M 0x04
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#define SIS_CMD_QUEUE_SIZE_2M 0x08
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#define SIS_CMD_QUEUE_SIZE_4M 0x0C
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#define SIS_CMD_QUEUE_RESET 0x01
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#define SIS_CMD_AUTO_CORR 0x02
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#define SIS_CMD_QUEUE_SIZE_Z7_64k 0x00 /* XGI Z7 */
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#define SIS_CMD_QUEUE_SIZE_Z7_128k 0x04
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#define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */
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#define SIS_MODE_SELECT_CRT2 0x02
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#define SIS_VB_OUTPUT_COMPOSITE 0x04
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#define SIS_VB_OUTPUT_SVIDEO 0x08
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#define SIS_VB_OUTPUT_SCART 0x10
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#define SIS_VB_OUTPUT_LCD 0x20
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#define SIS_VB_OUTPUT_CRT2 0x40
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#define SIS_VB_OUTPUT_HIVISION 0x80
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#define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */
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#define SIS_DRIVER_MODE 0x40
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#define SIS_VB_COMPOSITE 0x01 /* CR32 */
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#define SIS_VB_SVIDEO 0x02
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#define SIS_VB_SCART 0x04
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#define SIS_VB_LCD 0x08
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#define SIS_VB_CRT2 0x10
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#define SIS_CRT1 0x20
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#define SIS_VB_HIVISION 0x40
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#define SIS_VB_YPBPR 0x80
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#define SIS_VB_TV (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \
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SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR)
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#define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 (< SiS 660) */
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#define SIS_EXTERNAL_CHIP_SIS301 0x01 /* in CR37 << 1 ! */
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#define SIS_EXTERNAL_CHIP_LVDS 0x02
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#define SIS_EXTERNAL_CHIP_TRUMPION 0x03
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#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04
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#define SIS_EXTERNAL_CHIP_CHRONTEL 0x05
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#define SIS310_EXTERNAL_CHIP_LVDS 0x02
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#define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03
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#define SIS_AGP_2X 0x20 /* CR48 */
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/* vbflags, private entries (others in sisfb.h) */
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#define VB_CONEXANT 0x00000800 /* 661 series only */
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#define VB_TRUMPION VB_CONEXANT /* 300 series only */
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#define VB_302ELV 0x00004000
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#define VB_301 0x00100000 /* Video bridge type */
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#define VB_301B 0x00200000
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#define VB_302B 0x00400000
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#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */
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#define VB_LVDS 0x01000000
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#define VB_CHRONTEL 0x02000000
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#define VB_301LV 0x04000000
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#define VB_302LV 0x08000000
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#define VB_301C 0x10000000
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#define VB_SISBRIDGE (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV)
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#define VB_VIDEOBRIDGE (VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT)
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/* vbflags2 (static stuff only!) */
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#define VB2_SISUMC 0x00000001
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#define VB2_301 0x00000002 /* Video bridge type */
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#define VB2_301B 0x00000004
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#define VB2_301C 0x00000008
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#define VB2_307T 0x00000010
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#define VB2_302B 0x00000800
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#define VB2_301LV 0x00001000
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#define VB2_302LV 0x00002000
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#define VB2_302ELV 0x00004000
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#define VB2_307LV 0x00008000
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#define VB2_30xBDH 0x08000000 /* 30xB DH version (w/o LCD support) */
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#define VB2_CONEXANT 0x10000000
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#define VB2_TRUMPION 0x20000000
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#define VB2_LVDS 0x40000000
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#define VB2_CHRONTEL 0x80000000
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#define VB2_SISLVDSBRIDGE (VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)
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#define VB2_SISTMDSBRIDGE (VB2_301 | VB2_301B | VB2_301C | VB2_302B | VB2_307T)
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#define VB2_SISBRIDGE (VB2_SISLVDSBRIDGE | VB2_SISTMDSBRIDGE)
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#define VB2_SISTMDSLCDABRIDGE (VB2_301C | VB2_307T)
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#define VB2_SISLCDABRIDGE (VB2_SISTMDSLCDABRIDGE | VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)
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#define VB2_SISHIVISIONBRIDGE (VB2_301 | VB2_301B | VB2_302B)
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#define VB2_SISYPBPRBRIDGE (VB2_301C | VB2_307T | VB2_SISLVDSBRIDGE)
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#define VB2_SISYPBPRARBRIDGE (VB2_301C | VB2_307T | VB2_307LV)
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#define VB2_SISTAP4SCALER (VB2_301C | VB2_307T | VB2_302ELV | VB2_307LV)
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#define VB2_SISTVBRIDGE (VB2_SISHIVISIONBRIDGE | VB2_SISYPBPRBRIDGE)
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#define VB2_SISVGA2BRIDGE (VB2_301 | VB2_301B | VB2_301C | VB2_302B | VB2_307T)
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#define VB2_VIDEOBRIDGE (VB2_SISBRIDGE | VB2_LVDS | VB2_CHRONTEL | VB2_CONEXANT)
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#define VB2_30xB (VB2_301B | VB2_301C | VB2_302B | VB2_307T)
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#define VB2_30xBLV (VB2_30xB | VB2_SISLVDSBRIDGE)
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#define VB2_30xC (VB2_301C | VB2_307T)
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#define VB2_30xCLV (VB2_301C | VB2_307T | VB2_302ELV| VB2_307LV)
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#define VB2_SISEMIBRIDGE (VB2_302LV | VB2_302ELV | VB2_307LV)
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#define VB2_LCD162MHZBRIDGE (VB2_301C | VB2_307T)
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#define VB2_LCDOVER1280BRIDGE (VB2_301C | VB2_307T | VB2_302LV | VB2_302ELV | VB2_307LV)
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#define VB2_LCDOVER1600BRIDGE (VB2_307T | VB2_307LV)
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#define VB2_RAMDAC202MHZBRIDGE (VB2_301C | VB2_307T)
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/* I/O port access functions */
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void SiS_SetReg(SISIOADDRESS, u8, u8);
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void SiS_SetRegByte(SISIOADDRESS, u8);
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void SiS_SetRegShort(SISIOADDRESS, u16);
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void SiS_SetRegLong(SISIOADDRESS, u32);
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void SiS_SetRegANDOR(SISIOADDRESS, u8, u8, u8);
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void SiS_SetRegAND(SISIOADDRESS, u8, u8);
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void SiS_SetRegOR(SISIOADDRESS, u8, u8);
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u8 SiS_GetReg(SISIOADDRESS, u8);
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u8 SiS_GetRegByte(SISIOADDRESS);
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u16 SiS_GetRegShort(SISIOADDRESS);
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u32 SiS_GetRegLong(SISIOADDRESS);
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/* MMIO access macros */
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#define MMIO_IN8(base, offset) readb((base+offset))
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#define MMIO_IN16(base, offset) readw((base+offset))
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#define MMIO_IN32(base, offset) readl((base+offset))
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#define MMIO_OUT8(base, offset, val) writeb(((u8)(val)), (base+offset))
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#define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset))
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#define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))
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/* Queue control MMIO registers */
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#define Q_BASE_ADDR 0x85C0 /* Base address of software queue */
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#define Q_WRITE_PTR 0x85C4 /* Current write pointer */
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#define Q_READ_PTR 0x85C8 /* Current read pointer */
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#define Q_STATUS 0x85CC /* queue status */
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#define MMIO_QUEUE_PHYBASE Q_BASE_ADDR
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#define MMIO_QUEUE_WRITEPORT Q_WRITE_PTR
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#define MMIO_QUEUE_READPORT Q_READ_PTR
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#ifndef FB_BLANK_UNBLANK
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#define FB_BLANK_UNBLANK 0
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#endif
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#ifndef FB_BLANK_NORMAL
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#define FB_BLANK_NORMAL 1
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#endif
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#ifndef FB_BLANK_VSYNC_SUSPEND
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#define FB_BLANK_VSYNC_SUSPEND 2
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#endif
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#ifndef FB_BLANK_HSYNC_SUSPEND
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#define FB_BLANK_HSYNC_SUSPEND 3
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#endif
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#ifndef FB_BLANK_POWERDOWN
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#define FB_BLANK_POWERDOWN 4
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#endif
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enum _SIS_LCD_TYPE {
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LCD_INVALID = 0,
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LCD_800x600,
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LCD_1024x768,
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LCD_1280x1024,
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LCD_1280x960,
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LCD_640x480,
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LCD_1600x1200,
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LCD_1920x1440,
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LCD_2048x1536,
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LCD_320x240, /* FSTN */
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LCD_1400x1050,
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LCD_1152x864,
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LCD_1152x768,
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LCD_1280x768,
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LCD_1024x600,
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LCD_320x240_2, /* DSTN */
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LCD_320x240_3, /* DSTN */
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LCD_848x480,
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LCD_1280x800,
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LCD_1680x1050,
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LCD_1280x720,
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LCD_1280x854,
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LCD_CUSTOM,
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LCD_UNKNOWN
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};
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enum _SIS_CMDTYPE {
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MMIO_CMD = 0,
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AGP_CMD_QUEUE,
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VM_CMD_QUEUE,
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};
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struct SIS_OH {
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struct SIS_OH *poh_next;
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struct SIS_OH *poh_prev;
|
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u32 offset;
|
|
u32 size;
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};
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|
|
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struct SIS_OHALLOC {
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struct SIS_OHALLOC *poha_next;
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struct SIS_OH aoh[1];
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};
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struct SIS_HEAP {
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struct SIS_OH oh_free;
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struct SIS_OH oh_used;
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struct SIS_OH *poh_freelist;
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struct SIS_OHALLOC *poha_chain;
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u32 max_freesize;
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struct sis_video_info *vinfo;
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};
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|
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/* Our "par" */
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struct sis_video_info {
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int cardnumber;
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struct fb_info *memyselfandi;
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|
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struct SiS_Private SiS_Pr;
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|
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struct sisfb_info sisfbinfo; /* For ioctl SISFB_GET_INFO */
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|
|
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struct fb_var_screeninfo default_var;
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|
|
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struct fb_fix_screeninfo sisfb_fix;
|
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u32 pseudo_palette[16];
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|
|
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struct sisfb_monitor {
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u16 hmin;
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|
u16 hmax;
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|
u16 vmin;
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u16 vmax;
|
|
u32 dclockmax;
|
|
u8 feature;
|
|
bool datavalid;
|
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} sisfb_thismonitor;
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|
|
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unsigned short chip_id; /* PCI ID of chip */
|
|
unsigned short chip_vendor; /* PCI ID of vendor */
|
|
char myid[40];
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|
|
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struct pci_dev *nbridge;
|
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struct pci_dev *lpcdev;
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|
|
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int mni; /* Mode number index */
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|
|
|
unsigned long video_size;
|
|
unsigned long video_base;
|
|
unsigned long mmio_size;
|
|
unsigned long mmio_base;
|
|
unsigned long vga_base;
|
|
|
|
unsigned long video_offset;
|
|
|
|
unsigned long UMAsize, LFBsize;
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|
|
|
void __iomem *video_vbase;
|
|
void __iomem *mmio_vbase;
|
|
|
|
unsigned char *bios_abase;
|
|
|
|
int mtrr;
|
|
|
|
u32 sisfb_mem;
|
|
|
|
u32 sisfb_parm_mem;
|
|
int sisfb_accel;
|
|
int sisfb_ypan;
|
|
int sisfb_max;
|
|
int sisfb_userom;
|
|
int sisfb_useoem;
|
|
int sisfb_mode_idx;
|
|
int sisfb_parm_rate;
|
|
int sisfb_crt1off;
|
|
int sisfb_forcecrt1;
|
|
int sisfb_crt2type;
|
|
int sisfb_crt2flags;
|
|
int sisfb_dstn;
|
|
int sisfb_fstn;
|
|
int sisfb_tvplug;
|
|
int sisfb_tvstd;
|
|
int sisfb_nocrt2rate;
|
|
|
|
u32 heapstart; /* offset */
|
|
void __iomem *sisfb_heap_start; /* address */
|
|
void __iomem *sisfb_heap_end; /* address */
|
|
u32 sisfb_heap_size;
|
|
int havenoheap;
|
|
|
|
struct SIS_HEAP sisfb_heap; /* This card's vram heap */
|
|
|
|
int video_bpp;
|
|
int video_cmap_len;
|
|
int video_width;
|
|
int video_height;
|
|
unsigned int refresh_rate;
|
|
|
|
unsigned int chip;
|
|
unsigned int chip_real_id;
|
|
u8 revision_id;
|
|
int sisvga_enabled; /* PCI device was enabled */
|
|
|
|
int video_linelength; /* real pitch */
|
|
int scrnpitchCRT1; /* pitch regarding interlace */
|
|
|
|
u16 DstColor; /* For 2d acceleration */
|
|
u32 SiS310_AccelDepth;
|
|
u32 CommandReg;
|
|
int cmdqueuelength; /* Current (for accel) */
|
|
u32 cmdQueueSize; /* Total size in KB */
|
|
|
|
spinlock_t lockaccel; /* Do not use outside of kernel! */
|
|
|
|
unsigned int pcibus;
|
|
unsigned int pcislot;
|
|
unsigned int pcifunc;
|
|
|
|
int accel;
|
|
int engineok;
|
|
|
|
u16 subsysvendor;
|
|
u16 subsysdevice;
|
|
|
|
u32 vbflags; /* Replacing deprecated stuff from above */
|
|
u32 currentvbflags;
|
|
u32 vbflags2;
|
|
|
|
int lcdxres, lcdyres;
|
|
int lcddefmodeidx, tvdefmodeidx, defmodeidx;
|
|
u32 CRT2LCDType; /* defined in "SIS_LCD_TYPE" */
|
|
u32 curFSTN, curDSTN;
|
|
|
|
int current_bpp;
|
|
int current_width;
|
|
int current_height;
|
|
int current_htotal;
|
|
int current_vtotal;
|
|
int current_linelength;
|
|
__u32 current_pixclock;
|
|
int current_refresh_rate;
|
|
|
|
unsigned int current_base;
|
|
|
|
u8 mode_no;
|
|
u8 rate_idx;
|
|
int modechanged;
|
|
unsigned char modeprechange;
|
|
|
|
u8 sisfb_lastrates[128];
|
|
|
|
int newrom;
|
|
int haveXGIROM;
|
|
int registered;
|
|
int warncount;
|
|
|
|
int sisvga_engine;
|
|
int hwcursor_size;
|
|
int CRT2_write_enable;
|
|
u8 caps;
|
|
|
|
u8 detectedpdc;
|
|
u8 detectedpdca;
|
|
u8 detectedlcda;
|
|
|
|
void __iomem *hwcursor_vbase;
|
|
|
|
int chronteltype;
|
|
int tvxpos, tvypos;
|
|
u8 p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02;
|
|
int tvx, tvy;
|
|
|
|
u8 sisfblocked;
|
|
|
|
struct sisfb_info sisfb_infoblock;
|
|
|
|
struct sisfb_cmd sisfb_command;
|
|
|
|
u32 sisfb_id;
|
|
|
|
u8 sisfb_can_post;
|
|
u8 sisfb_card_posted;
|
|
u8 sisfb_was_boot_device;
|
|
|
|
struct sis_video_info *next;
|
|
};
|
|
|
|
#endif
|