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cea62f9fee
This adds watchdog support the Fintek F81966 Super I/O chip. Testing was done on the Aaeon SSE-OPTI Signed-off-by: AaeonIot <sophiehu@aaeon.com.tw> Signed-off-by: Chia-Lin Kao (AceLan) <acelan.kao@canonical.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20211117024052.2427539-1-acelan.kao@canonical.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
667 lines
17 KiB
C
667 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2006 by Hans Edgington <hans@edgington.nl> *
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* Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com> *
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* Copyright (C) 2010 Giel van Schijndel <me@mortis.eu> *
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* *
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***************************************************************************/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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#define DRVNAME "f71808e_wdt"
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#define SIO_F71808FG_LD_WDT 0x07 /* Watchdog timer logical device */
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#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
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#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
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#define SIO_REG_LDSEL 0x07 /* Logical device select */
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#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
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#define SIO_REG_DEVREV 0x22 /* Device revision */
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#define SIO_REG_MANID 0x23 /* Fintek ID (2 bytes) */
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#define SIO_REG_CLOCK_SEL 0x26 /* Clock select */
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#define SIO_REG_ROM_ADDR_SEL 0x27 /* ROM address select */
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#define SIO_F81866_REG_PORT_SEL 0x27 /* F81866 Multi-Function Register */
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#define SIO_REG_TSI_LEVEL_SEL 0x28 /* TSI Level select */
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#define SIO_REG_MFUNCT1 0x29 /* Multi function select 1 */
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#define SIO_REG_MFUNCT2 0x2a /* Multi function select 2 */
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#define SIO_REG_MFUNCT3 0x2b /* Multi function select 3 */
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#define SIO_F81866_REG_GPIO1 0x2c /* F81866 GPIO1 Enable Register */
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#define SIO_REG_ENABLE 0x30 /* Logical device enable */
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#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
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#define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
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#define SIO_F71808_ID 0x0901 /* Chipset ID */
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#define SIO_F71858_ID 0x0507 /* Chipset ID */
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#define SIO_F71862_ID 0x0601 /* Chipset ID */
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#define SIO_F71868_ID 0x1106 /* Chipset ID */
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#define SIO_F71869_ID 0x0814 /* Chipset ID */
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#define SIO_F71869A_ID 0x1007 /* Chipset ID */
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#define SIO_F71882_ID 0x0541 /* Chipset ID */
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#define SIO_F71889_ID 0x0723 /* Chipset ID */
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#define SIO_F81803_ID 0x1210 /* Chipset ID */
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#define SIO_F81865_ID 0x0704 /* Chipset ID */
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#define SIO_F81866_ID 0x1010 /* Chipset ID */
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#define SIO_F81966_ID 0x1502 /* F81804 chipset ID, same for f81966 */
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#define F71808FG_REG_WDO_CONF 0xf0
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#define F71808FG_REG_WDT_CONF 0xf5
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#define F71808FG_REG_WD_TIME 0xf6
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#define F71808FG_FLAG_WDOUT_EN 7
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#define F71808FG_FLAG_WDTMOUT_STS 6
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#define F71808FG_FLAG_WD_EN 5
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#define F71808FG_FLAG_WD_PULSE 4
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#define F71808FG_FLAG_WD_UNIT 3
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#define F81865_REG_WDO_CONF 0xfa
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#define F81865_FLAG_WDOUT_EN 0
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/* Default values */
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#define WATCHDOG_TIMEOUT 60 /* 1 minute default timeout */
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#define WATCHDOG_MAX_TIMEOUT (60 * 255)
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#define WATCHDOG_PULSE_WIDTH 125 /* 125 ms, default pulse width for
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watchdog signal */
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#define WATCHDOG_F71862FG_PIN 63 /* default watchdog reset output
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pin number 63 */
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static unsigned short force_id;
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module_param(force_id, ushort, 0);
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MODULE_PARM_DESC(force_id, "Override the detected device ID");
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static int timeout = WATCHDOG_TIMEOUT; /* default timeout in seconds */
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module_param(timeout, int, 0);
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MODULE_PARM_DESC(timeout,
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"Watchdog timeout in seconds. 1<= timeout <="
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__MODULE_STRING(WATCHDOG_MAX_TIMEOUT) " (default="
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__MODULE_STRING(WATCHDOG_TIMEOUT) ")");
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static unsigned int pulse_width = WATCHDOG_PULSE_WIDTH;
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module_param(pulse_width, uint, 0);
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MODULE_PARM_DESC(pulse_width,
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"Watchdog signal pulse width. 0(=level), 1, 25, 30, 125, 150, 5000 or 6000 ms"
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" (default=" __MODULE_STRING(WATCHDOG_PULSE_WIDTH) ")");
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static unsigned int f71862fg_pin = WATCHDOG_F71862FG_PIN;
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module_param(f71862fg_pin, uint, 0);
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MODULE_PARM_DESC(f71862fg_pin,
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"Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63"
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" (default=" __MODULE_STRING(WATCHDOG_F71862FG_PIN)")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0444);
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MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
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static unsigned int start_withtimeout;
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module_param(start_withtimeout, uint, 0);
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MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
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" given initial timeout. Zero (default) disables this feature.");
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enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
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f81803, f81865, f81866, f81966};
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static const char * const fintek_wdt_names[] = {
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"f71808fg",
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"f71858fg",
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"f71862fg",
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"f71868",
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"f71869",
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"f71882fg",
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"f71889fg",
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"f81803",
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"f81865",
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"f81866",
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"f81966"
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};
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/* Super-I/O Function prototypes */
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static inline int superio_inb(int base, int reg);
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static inline int superio_inw(int base, int reg);
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static inline void superio_outb(int base, int reg, u8 val);
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static inline void superio_set_bit(int base, int reg, int bit);
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static inline void superio_clear_bit(int base, int reg, int bit);
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static inline int superio_enter(int base);
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static inline void superio_select(int base, int ld);
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static inline void superio_exit(int base);
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struct fintek_wdt {
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struct watchdog_device wdd;
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unsigned short sioaddr;
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enum chips type;
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struct watchdog_info ident;
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u8 timer_val; /* content for the wd_time register */
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char minutes_mode;
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u8 pulse_val; /* pulse width flag */
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char pulse_mode; /* enable pulse output mode? */
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};
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struct fintek_wdt_pdata {
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enum chips type;
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};
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/* Super I/O functions */
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static inline int superio_inb(int base, int reg)
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{
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outb(reg, base);
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return inb(base + 1);
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}
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static int superio_inw(int base, int reg)
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{
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int val;
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val = superio_inb(base, reg) << 8;
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val |= superio_inb(base, reg + 1);
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return val;
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}
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static inline void superio_outb(int base, int reg, u8 val)
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{
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outb(reg, base);
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outb(val, base + 1);
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}
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static inline void superio_set_bit(int base, int reg, int bit)
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{
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unsigned long val = superio_inb(base, reg);
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__set_bit(bit, &val);
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superio_outb(base, reg, val);
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}
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static inline void superio_clear_bit(int base, int reg, int bit)
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{
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unsigned long val = superio_inb(base, reg);
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__clear_bit(bit, &val);
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superio_outb(base, reg, val);
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}
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static inline int superio_enter(int base)
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{
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/* Don't step on other drivers' I/O space by accident */
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if (!request_muxed_region(base, 2, DRVNAME)) {
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pr_err("I/O address 0x%04x already in use\n", (int)base);
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return -EBUSY;
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}
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/* according to the datasheet the key must be sent twice! */
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outb(SIO_UNLOCK_KEY, base);
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outb(SIO_UNLOCK_KEY, base);
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return 0;
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}
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static inline void superio_select(int base, int ld)
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{
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outb(SIO_REG_LDSEL, base);
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outb(ld, base + 1);
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}
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static inline void superio_exit(int base)
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{
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outb(SIO_LOCK_KEY, base);
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release_region(base, 2);
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}
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static int fintek_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
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{
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struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
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if (timeout > 0xff) {
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wd->timer_val = DIV_ROUND_UP(timeout, 60);
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wd->minutes_mode = true;
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timeout = wd->timer_val * 60;
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} else {
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wd->timer_val = timeout;
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wd->minutes_mode = false;
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}
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wdd->timeout = timeout;
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return 0;
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}
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static int fintek_wdt_set_pulse_width(struct fintek_wdt *wd, unsigned int pw)
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{
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unsigned int t1 = 25, t2 = 125, t3 = 5000;
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if (wd->type == f71868) {
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t1 = 30;
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t2 = 150;
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t3 = 6000;
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}
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if (pw <= 1) {
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wd->pulse_val = 0;
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} else if (pw <= t1) {
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wd->pulse_val = 1;
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} else if (pw <= t2) {
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wd->pulse_val = 2;
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} else if (pw <= t3) {
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wd->pulse_val = 3;
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} else {
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pr_err("pulse width out of range\n");
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return -EINVAL;
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}
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wd->pulse_mode = pw;
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return 0;
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}
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static int fintek_wdt_keepalive(struct watchdog_device *wdd)
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{
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struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
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int err;
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err = superio_enter(wd->sioaddr);
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if (err)
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return err;
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superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
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if (wd->minutes_mode)
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/* select minutes for timer units */
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superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
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F71808FG_FLAG_WD_UNIT);
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else
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/* select seconds for timer units */
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superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
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F71808FG_FLAG_WD_UNIT);
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/* Set timer value */
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superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME,
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wd->timer_val);
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superio_exit(wd->sioaddr);
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return 0;
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}
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static int fintek_wdt_start(struct watchdog_device *wdd)
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{
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struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
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int err;
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u8 tmp;
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/* Make sure we don't die as soon as the watchdog is enabled below */
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err = fintek_wdt_keepalive(wdd);
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if (err)
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return err;
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err = superio_enter(wd->sioaddr);
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if (err)
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return err;
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superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
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/* Watchdog pin configuration */
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switch (wd->type) {
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case f71808fg:
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/* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */
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superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT2, 3);
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superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 3);
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break;
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case f71862fg:
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if (f71862fg_pin == 63) {
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/* SPI must be disabled first to use this pin! */
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superio_clear_bit(wd->sioaddr, SIO_REG_ROM_ADDR_SEL, 6);
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superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT3, 4);
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} else if (f71862fg_pin == 56) {
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superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);
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}
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break;
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case f71868:
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case f71869:
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/* GPIO14 --> WDTRST# */
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superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT1, 4);
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break;
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case f71882fg:
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/* Set pin 56 to WDTRST# */
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superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);
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break;
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case f71889fg:
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/* set pin 40 to WDTRST# */
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superio_outb(wd->sioaddr, SIO_REG_MFUNCT3,
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superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf);
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break;
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case f81803:
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/* Enable TSI Level register bank */
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superio_clear_bit(wd->sioaddr, SIO_REG_CLOCK_SEL, 3);
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/* Set pin 27 to WDTRST# */
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superio_outb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &
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superio_inb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL));
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break;
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case f81865:
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/* Set pin 70 to WDTRST# */
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superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 5);
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break;
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case f81866:
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case f81966:
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/*
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* GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
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* The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
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* BIT5: 0 -> WDTRST#
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* 1 -> GPIO15
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*/
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tmp = superio_inb(wd->sioaddr, SIO_F81866_REG_PORT_SEL);
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tmp &= ~(BIT(3) | BIT(0));
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tmp |= BIT(2);
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superio_outb(wd->sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
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superio_clear_bit(wd->sioaddr, SIO_F81866_REG_GPIO1, 5);
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break;
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default:
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/*
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* 'default' label to shut up the compiler and catch
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* programmer errors
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*/
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err = -ENODEV;
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goto exit_superio;
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}
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superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
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superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);
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if (wd->type == f81865 || wd->type == f81866 || wd->type == f81966)
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superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF,
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F81865_FLAG_WDOUT_EN);
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else
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superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF,
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F71808FG_FLAG_WDOUT_EN);
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superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
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F71808FG_FLAG_WD_EN);
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if (wd->pulse_mode) {
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/* Select "pulse" output mode with given duration */
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u8 wdt_conf = superio_inb(wd->sioaddr,
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F71808FG_REG_WDT_CONF);
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/* Set WD_PSWIDTH bits (1:0) */
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wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_val & 0x03);
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/* Set WD_PULSE to "pulse" mode */
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wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE);
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superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF,
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wdt_conf);
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} else {
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/* Select "level" output mode */
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superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
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F71808FG_FLAG_WD_PULSE);
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}
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exit_superio:
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superio_exit(wd->sioaddr);
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return err;
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}
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static int fintek_wdt_stop(struct watchdog_device *wdd)
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{
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struct fintek_wdt *wd = watchdog_get_drvdata(wdd);
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int err;
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err = superio_enter(wd->sioaddr);
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if (err)
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return err;
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superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
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superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
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F71808FG_FLAG_WD_EN);
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superio_exit(wd->sioaddr);
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return 0;
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}
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static bool fintek_wdt_is_running(struct fintek_wdt *wd, u8 wdt_conf)
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{
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return (superio_inb(wd->sioaddr, SIO_REG_ENABLE) & BIT(0))
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&& (wdt_conf & BIT(F71808FG_FLAG_WD_EN));
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}
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static const struct watchdog_ops fintek_wdt_ops = {
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.owner = THIS_MODULE,
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.start = fintek_wdt_start,
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.stop = fintek_wdt_stop,
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.ping = fintek_wdt_keepalive,
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.set_timeout = fintek_wdt_set_timeout,
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};
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static int fintek_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct fintek_wdt_pdata *pdata;
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struct watchdog_device *wdd;
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struct fintek_wdt *wd;
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int wdt_conf, err = 0;
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struct resource *res;
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int sioaddr;
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res = platform_get_resource(pdev, IORESOURCE_IO, 0);
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if (!res)
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return -ENXIO;
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sioaddr = res->start;
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wd = devm_kzalloc(dev, sizeof(*wd), GFP_KERNEL);
|
|
if (!wd)
|
|
return -ENOMEM;
|
|
|
|
pdata = dev->platform_data;
|
|
|
|
wd->type = pdata->type;
|
|
wd->sioaddr = sioaddr;
|
|
wd->ident.options = WDIOF_SETTIMEOUT
|
|
| WDIOF_MAGICCLOSE
|
|
| WDIOF_KEEPALIVEPING
|
|
| WDIOF_CARDRESET;
|
|
|
|
snprintf(wd->ident.identity,
|
|
sizeof(wd->ident.identity), "%s watchdog",
|
|
fintek_wdt_names[wd->type]);
|
|
|
|
err = superio_enter(sioaddr);
|
|
if (err)
|
|
return err;
|
|
superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
|
|
|
|
wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
|
|
|
|
/*
|
|
* We don't want WDTMOUT_STS to stick around till regular reboot.
|
|
* Write 1 to the bit to clear it to zero.
|
|
*/
|
|
superio_outb(sioaddr, F71808FG_REG_WDT_CONF,
|
|
wdt_conf | BIT(F71808FG_FLAG_WDTMOUT_STS));
|
|
|
|
wdd = &wd->wdd;
|
|
|
|
if (fintek_wdt_is_running(wd, wdt_conf))
|
|
set_bit(WDOG_HW_RUNNING, &wdd->status);
|
|
|
|
superio_exit(sioaddr);
|
|
|
|
wdd->parent = dev;
|
|
wdd->info = &wd->ident;
|
|
wdd->ops = &fintek_wdt_ops;
|
|
wdd->min_timeout = 1;
|
|
wdd->max_timeout = WATCHDOG_MAX_TIMEOUT;
|
|
|
|
watchdog_set_drvdata(wdd, wd);
|
|
watchdog_set_nowayout(wdd, nowayout);
|
|
watchdog_stop_on_unregister(wdd);
|
|
watchdog_stop_on_reboot(wdd);
|
|
watchdog_init_timeout(wdd, start_withtimeout ?: timeout, NULL);
|
|
|
|
if (wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS))
|
|
wdd->bootstatus = WDIOF_CARDRESET;
|
|
|
|
/*
|
|
* WATCHDOG_HANDLE_BOOT_ENABLED can result in keepalive being directly
|
|
* called without a set_timeout before, so it needs to be done here
|
|
* unconditionally.
|
|
*/
|
|
fintek_wdt_set_timeout(wdd, wdd->timeout);
|
|
fintek_wdt_set_pulse_width(wd, pulse_width);
|
|
|
|
if (start_withtimeout) {
|
|
err = fintek_wdt_start(wdd);
|
|
if (err) {
|
|
dev_err(dev, "cannot start watchdog timer\n");
|
|
return err;
|
|
}
|
|
|
|
set_bit(WDOG_HW_RUNNING, &wdd->status);
|
|
dev_info(dev, "watchdog started with initial timeout of %u sec\n",
|
|
start_withtimeout);
|
|
}
|
|
|
|
return devm_watchdog_register_device(dev, wdd);
|
|
}
|
|
|
|
static int __init fintek_wdt_find(int sioaddr)
|
|
{
|
|
enum chips type;
|
|
u16 devid;
|
|
int err = superio_enter(sioaddr);
|
|
if (err)
|
|
return err;
|
|
|
|
devid = superio_inw(sioaddr, SIO_REG_MANID);
|
|
if (devid != SIO_FINTEK_ID) {
|
|
pr_debug("Not a Fintek device\n");
|
|
err = -ENODEV;
|
|
goto exit;
|
|
}
|
|
|
|
devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID);
|
|
switch (devid) {
|
|
case SIO_F71808_ID:
|
|
type = f71808fg;
|
|
break;
|
|
case SIO_F71862_ID:
|
|
type = f71862fg;
|
|
break;
|
|
case SIO_F71868_ID:
|
|
type = f71868;
|
|
break;
|
|
case SIO_F71869_ID:
|
|
case SIO_F71869A_ID:
|
|
type = f71869;
|
|
break;
|
|
case SIO_F71882_ID:
|
|
type = f71882fg;
|
|
break;
|
|
case SIO_F71889_ID:
|
|
type = f71889fg;
|
|
break;
|
|
case SIO_F71858_ID:
|
|
/* Confirmed (by datasheet) not to have a watchdog. */
|
|
err = -ENODEV;
|
|
goto exit;
|
|
case SIO_F81803_ID:
|
|
type = f81803;
|
|
break;
|
|
case SIO_F81865_ID:
|
|
type = f81865;
|
|
break;
|
|
case SIO_F81866_ID:
|
|
type = f81866;
|
|
break;
|
|
case SIO_F81966_ID:
|
|
type = f81966;
|
|
break;
|
|
default:
|
|
pr_info("Unrecognized Fintek device: %04x\n",
|
|
(unsigned int)devid);
|
|
err = -ENODEV;
|
|
goto exit;
|
|
}
|
|
|
|
pr_info("Found %s watchdog chip, revision %d\n",
|
|
fintek_wdt_names[type],
|
|
(int)superio_inb(sioaddr, SIO_REG_DEVREV));
|
|
|
|
exit:
|
|
superio_exit(sioaddr);
|
|
return err ? err : type;
|
|
}
|
|
|
|
static struct platform_driver fintek_wdt_driver = {
|
|
.probe = fintek_wdt_probe,
|
|
.driver = {
|
|
.name = DRVNAME,
|
|
},
|
|
};
|
|
|
|
static struct platform_device *fintek_wdt_pdev;
|
|
|
|
static int __init fintek_wdt_init(void)
|
|
{
|
|
static const unsigned short addrs[] = { 0x2e, 0x4e };
|
|
struct fintek_wdt_pdata pdata;
|
|
struct resource wdt_res = {};
|
|
int ret;
|
|
int i;
|
|
|
|
if (f71862fg_pin != 63 && f71862fg_pin != 56) {
|
|
pr_err("Invalid argument f71862fg_pin=%d\n", f71862fg_pin);
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(addrs); i++) {
|
|
ret = fintek_wdt_find(addrs[i]);
|
|
if (ret >= 0)
|
|
break;
|
|
}
|
|
if (i == ARRAY_SIZE(addrs))
|
|
return ret;
|
|
|
|
pdata.type = ret;
|
|
|
|
platform_driver_register(&fintek_wdt_driver);
|
|
|
|
wdt_res.name = "superio port";
|
|
wdt_res.flags = IORESOURCE_IO;
|
|
wdt_res.start = addrs[i];
|
|
wdt_res.end = addrs[i] + 1;
|
|
|
|
fintek_wdt_pdev = platform_device_register_resndata(NULL, DRVNAME, -1,
|
|
&wdt_res, 1,
|
|
&pdata, sizeof(pdata));
|
|
if (IS_ERR(fintek_wdt_pdev)) {
|
|
platform_driver_unregister(&fintek_wdt_driver);
|
|
return PTR_ERR(fintek_wdt_pdev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit fintek_wdt_exit(void)
|
|
{
|
|
platform_device_unregister(fintek_wdt_pdev);
|
|
platform_driver_unregister(&fintek_wdt_driver);
|
|
}
|
|
|
|
MODULE_DESCRIPTION("F71808E Watchdog Driver");
|
|
MODULE_AUTHOR("Giel van Schijndel <me@mortis.eu>");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
module_init(fintek_wdt_init);
|
|
module_exit(fintek_wdt_exit);
|