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f7d344f218
Netlogic XLP was removed in commit 95b8a5e011
("MIPS: Remove NETLOGIC
support"). With those gone, the single platform left to support is
Cavium ThunderX2. Remove the Netlogic variant and DT support.
For simplicity, the existing kconfig name is retained.
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211109161325.2203564-1-robh@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
450 lines
11 KiB
C
450 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2003-2015 Broadcom Corporation
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* All Rights Reserved
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/interrupt.h>
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/* SPI Configuration Register */
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#define XLP_SPI_CONFIG 0x00
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#define XLP_SPI_CPHA BIT(0)
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#define XLP_SPI_CPOL BIT(1)
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#define XLP_SPI_CS_POL BIT(2)
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#define XLP_SPI_TXMISO_EN BIT(3)
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#define XLP_SPI_TXMOSI_EN BIT(4)
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#define XLP_SPI_RXMISO_EN BIT(5)
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#define XLP_SPI_CS_LSBFE BIT(10)
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#define XLP_SPI_RXCAP_EN BIT(11)
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/* SPI Frequency Divider Register */
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#define XLP_SPI_FDIV 0x04
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/* SPI Command Register */
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#define XLP_SPI_CMD 0x08
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#define XLP_SPI_CMD_IDLE_MASK 0x0
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#define XLP_SPI_CMD_TX_MASK 0x1
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#define XLP_SPI_CMD_RX_MASK 0x2
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#define XLP_SPI_CMD_TXRX_MASK 0x3
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#define XLP_SPI_CMD_CONT BIT(4)
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#define XLP_SPI_XFR_BITCNT_SHIFT 16
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/* SPI Status Register */
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#define XLP_SPI_STATUS 0x0c
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#define XLP_SPI_XFR_PENDING BIT(0)
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#define XLP_SPI_XFR_DONE BIT(1)
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#define XLP_SPI_TX_INT BIT(2)
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#define XLP_SPI_RX_INT BIT(3)
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#define XLP_SPI_TX_UF BIT(4)
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#define XLP_SPI_RX_OF BIT(5)
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#define XLP_SPI_STAT_MASK 0x3f
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/* SPI Interrupt Enable Register */
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#define XLP_SPI_INTR_EN 0x10
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#define XLP_SPI_INTR_DONE BIT(0)
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#define XLP_SPI_INTR_TXTH BIT(1)
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#define XLP_SPI_INTR_RXTH BIT(2)
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#define XLP_SPI_INTR_TXUF BIT(3)
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#define XLP_SPI_INTR_RXOF BIT(4)
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/* SPI FIFO Threshold Register */
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#define XLP_SPI_FIFO_THRESH 0x14
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/* SPI FIFO Word Count Register */
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#define XLP_SPI_FIFO_WCNT 0x18
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#define XLP_SPI_RXFIFO_WCNT_MASK 0xf
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#define XLP_SPI_TXFIFO_WCNT_MASK 0xf0
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#define XLP_SPI_TXFIFO_WCNT_SHIFT 4
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/* SPI Transmit Data FIFO Register */
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#define XLP_SPI_TXDATA_FIFO 0x1c
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/* SPI Receive Data FIFO Register */
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#define XLP_SPI_RXDATA_FIFO 0x20
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/* SPI System Control Register */
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#define XLP_SPI_SYSCTRL 0x100
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#define XLP_SPI_SYS_RESET BIT(0)
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#define XLP_SPI_SYS_CLKDIS BIT(1)
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#define XLP_SPI_SYS_PMEN BIT(8)
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#define SPI_CS_OFFSET 0x40
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#define XLP_SPI_TXRXTH 0x80
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#define XLP_SPI_FIFO_SIZE 8
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#define XLP_SPI_MAX_CS 4
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#define XLP_SPI_DEFAULT_FREQ 133333333
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#define XLP_SPI_FDIV_MIN 4
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#define XLP_SPI_FDIV_MAX 65535
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/*
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* SPI can transfer only 28 bytes properly at a time. So split the
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* transfer into 28 bytes size.
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*/
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#define XLP_SPI_XFER_SIZE 28
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struct xlp_spi_priv {
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struct device dev; /* device structure */
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void __iomem *base; /* spi registers base address */
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const u8 *tx_buf; /* tx data buffer */
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u8 *rx_buf; /* rx data buffer */
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int tx_len; /* tx xfer length */
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int rx_len; /* rx xfer length */
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int txerrors; /* TXFIFO underflow count */
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int rxerrors; /* RXFIFO overflow count */
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int cs; /* slave device chip select */
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u32 spi_clk; /* spi clock frequency */
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bool cmd_cont; /* cs active */
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struct completion done; /* completion notification */
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};
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static inline u32 xlp_spi_reg_read(struct xlp_spi_priv *priv,
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int cs, int regoff)
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{
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return readl(priv->base + regoff + cs * SPI_CS_OFFSET);
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}
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static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs,
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int regoff, u32 val)
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{
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writel(val, priv->base + regoff + cs * SPI_CS_OFFSET);
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}
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static inline void xlp_spi_sysctl_write(struct xlp_spi_priv *priv,
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int regoff, u32 val)
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{
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writel(val, priv->base + regoff);
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}
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/*
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* Setup global SPI_SYSCTRL register for all SPI channels.
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*/
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static void xlp_spi_sysctl_setup(struct xlp_spi_priv *xspi)
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{
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int cs;
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for (cs = 0; cs < XLP_SPI_MAX_CS; cs++)
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xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL,
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XLP_SPI_SYS_RESET << cs);
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xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, XLP_SPI_SYS_PMEN);
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}
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static int xlp_spi_setup(struct spi_device *spi)
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{
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struct xlp_spi_priv *xspi;
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u32 fdiv, cfg;
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int cs;
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xspi = spi_master_get_devdata(spi->master);
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cs = spi->chip_select;
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/*
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* The value of fdiv must be between 4 and 65535.
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*/
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fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz);
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if (fdiv > XLP_SPI_FDIV_MAX)
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fdiv = XLP_SPI_FDIV_MAX;
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else if (fdiv < XLP_SPI_FDIV_MIN)
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fdiv = XLP_SPI_FDIV_MIN;
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xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv);
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xlp_spi_reg_write(xspi, cs, XLP_SPI_FIFO_THRESH, XLP_SPI_TXRXTH);
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cfg = xlp_spi_reg_read(xspi, cs, XLP_SPI_CONFIG);
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if (spi->mode & SPI_CPHA)
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cfg |= XLP_SPI_CPHA;
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else
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cfg &= ~XLP_SPI_CPHA;
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if (spi->mode & SPI_CPOL)
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cfg |= XLP_SPI_CPOL;
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else
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cfg &= ~XLP_SPI_CPOL;
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if (!(spi->mode & SPI_CS_HIGH))
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cfg |= XLP_SPI_CS_POL;
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else
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cfg &= ~XLP_SPI_CS_POL;
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if (spi->mode & SPI_LSB_FIRST)
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cfg |= XLP_SPI_CS_LSBFE;
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else
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cfg &= ~XLP_SPI_CS_LSBFE;
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cfg |= XLP_SPI_TXMOSI_EN | XLP_SPI_RXMISO_EN;
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if (fdiv == 4)
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cfg |= XLP_SPI_RXCAP_EN;
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xlp_spi_reg_write(xspi, cs, XLP_SPI_CONFIG, cfg);
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return 0;
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}
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static void xlp_spi_read_rxfifo(struct xlp_spi_priv *xspi)
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{
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u32 rx_data, rxfifo_cnt;
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int i, j, nbytes;
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rxfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
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rxfifo_cnt &= XLP_SPI_RXFIFO_WCNT_MASK;
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while (rxfifo_cnt) {
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rx_data = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_RXDATA_FIFO);
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j = 0;
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nbytes = min(xspi->rx_len, 4);
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for (i = nbytes - 1; i >= 0; i--, j++)
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xspi->rx_buf[i] = (rx_data >> (j * 8)) & 0xff;
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xspi->rx_len -= nbytes;
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xspi->rx_buf += nbytes;
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rxfifo_cnt--;
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}
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}
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static void xlp_spi_fill_txfifo(struct xlp_spi_priv *xspi)
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{
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u32 tx_data, txfifo_cnt;
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int i, j, nbytes;
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txfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
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txfifo_cnt &= XLP_SPI_TXFIFO_WCNT_MASK;
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txfifo_cnt >>= XLP_SPI_TXFIFO_WCNT_SHIFT;
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while (xspi->tx_len && (txfifo_cnt < XLP_SPI_FIFO_SIZE)) {
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j = 0;
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tx_data = 0;
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nbytes = min(xspi->tx_len, 4);
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for (i = nbytes - 1; i >= 0; i--, j++)
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tx_data |= xspi->tx_buf[i] << (j * 8);
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xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_TXDATA_FIFO, tx_data);
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xspi->tx_len -= nbytes;
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xspi->tx_buf += nbytes;
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txfifo_cnt++;
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}
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}
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static irqreturn_t xlp_spi_interrupt(int irq, void *dev_id)
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{
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struct xlp_spi_priv *xspi = dev_id;
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u32 stat;
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stat = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_STATUS) &
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XLP_SPI_STAT_MASK;
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if (!stat)
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return IRQ_NONE;
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if (stat & XLP_SPI_TX_INT) {
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if (xspi->tx_len)
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xlp_spi_fill_txfifo(xspi);
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if (stat & XLP_SPI_TX_UF)
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xspi->txerrors++;
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}
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if (stat & XLP_SPI_RX_INT) {
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if (xspi->rx_len)
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xlp_spi_read_rxfifo(xspi);
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if (stat & XLP_SPI_RX_OF)
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xspi->rxerrors++;
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}
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/* write status back to clear interrupts */
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xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_STATUS, stat);
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if (stat & XLP_SPI_XFR_DONE)
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complete(&xspi->done);
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return IRQ_HANDLED;
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}
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static void xlp_spi_send_cmd(struct xlp_spi_priv *xspi, int xfer_len,
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int cmd_cont)
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{
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u32 cmd = 0;
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if (xspi->tx_buf)
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cmd |= XLP_SPI_CMD_TX_MASK;
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if (xspi->rx_buf)
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cmd |= XLP_SPI_CMD_RX_MASK;
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if (cmd_cont)
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cmd |= XLP_SPI_CMD_CONT;
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cmd |= ((xfer_len * 8 - 1) << XLP_SPI_XFR_BITCNT_SHIFT);
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xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_CMD, cmd);
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}
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static int xlp_spi_xfer_block(struct xlp_spi_priv *xs,
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const unsigned char *tx_buf,
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unsigned char *rx_buf, int xfer_len, int cmd_cont)
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{
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int timeout;
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u32 intr_mask = 0;
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xs->tx_buf = tx_buf;
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xs->rx_buf = rx_buf;
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xs->tx_len = (xs->tx_buf == NULL) ? 0 : xfer_len;
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xs->rx_len = (xs->rx_buf == NULL) ? 0 : xfer_len;
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xs->txerrors = xs->rxerrors = 0;
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/* fill TXDATA_FIFO, then send the CMD */
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if (xs->tx_len)
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xlp_spi_fill_txfifo(xs);
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xlp_spi_send_cmd(xs, xfer_len, cmd_cont);
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/*
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* We are getting some spurious tx interrupts, so avoid enabling
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* tx interrupts when only rx is in process.
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* Enable all the interrupts in tx case.
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*/
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if (xs->tx_len)
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intr_mask |= XLP_SPI_INTR_TXTH | XLP_SPI_INTR_TXUF |
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XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
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else
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intr_mask |= XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
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intr_mask |= XLP_SPI_INTR_DONE;
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xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, intr_mask);
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timeout = wait_for_completion_timeout(&xs->done,
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msecs_to_jiffies(1000));
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/* Disable interrupts */
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xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, 0x0);
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if (!timeout) {
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dev_err(&xs->dev, "xfer timedout!\n");
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goto out;
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}
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if (xs->txerrors || xs->rxerrors)
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dev_err(&xs->dev, "Over/Underflow rx %d tx %d xfer %d!\n",
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xs->rxerrors, xs->txerrors, xfer_len);
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return xfer_len;
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out:
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return -ETIMEDOUT;
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}
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static int xlp_spi_txrx_bufs(struct xlp_spi_priv *xs, struct spi_transfer *t)
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{
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int bytesleft, sz;
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unsigned char *rx_buf;
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const unsigned char *tx_buf;
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tx_buf = t->tx_buf;
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rx_buf = t->rx_buf;
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bytesleft = t->len;
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while (bytesleft) {
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if (bytesleft > XLP_SPI_XFER_SIZE)
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sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
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XLP_SPI_XFER_SIZE, 1);
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else
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sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
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bytesleft, xs->cmd_cont);
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if (sz < 0)
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return sz;
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bytesleft -= sz;
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if (tx_buf)
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tx_buf += sz;
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if (rx_buf)
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rx_buf += sz;
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}
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return bytesleft;
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}
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static int xlp_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct xlp_spi_priv *xspi = spi_master_get_devdata(master);
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int ret = 0;
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xspi->cs = spi->chip_select;
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xspi->dev = spi->dev;
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if (spi_transfer_is_last(master, t))
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xspi->cmd_cont = 0;
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else
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xspi->cmd_cont = 1;
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if (xlp_spi_txrx_bufs(xspi, t))
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ret = -EIO;
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spi_finalize_current_transfer(master);
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return ret;
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}
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static int xlp_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct xlp_spi_priv *xspi;
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struct clk *clk;
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int irq, err;
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xspi = devm_kzalloc(&pdev->dev, sizeof(*xspi), GFP_KERNEL);
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if (!xspi)
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return -ENOMEM;
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xspi->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(xspi->base))
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return PTR_ERR(xspi->base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0,
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pdev->name, xspi);
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if (err) {
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dev_err(&pdev->dev, "unable to request irq %d\n", irq);
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return err;
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}
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "could not get spi clock\n");
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return PTR_ERR(clk);
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}
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xspi->spi_clk = clk_get_rate(clk);
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master = spi_alloc_master(&pdev->dev, 0);
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if (!master) {
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dev_err(&pdev->dev, "could not alloc master\n");
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return -ENOMEM;
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}
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master->bus_num = 0;
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master->num_chipselect = XLP_SPI_MAX_CS;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
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master->setup = xlp_spi_setup;
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master->transfer_one = xlp_spi_transfer_one;
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master->dev.of_node = pdev->dev.of_node;
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init_completion(&xspi->done);
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spi_master_set_devdata(master, xspi);
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xlp_spi_sysctl_setup(xspi);
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/* register spi controller */
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err = devm_spi_register_master(&pdev->dev, master);
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if (err) {
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dev_err(&pdev->dev, "spi register master failed!\n");
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spi_master_put(master);
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return err;
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}
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return 0;
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}
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#ifdef CONFIG_ACPI
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static const struct acpi_device_id xlp_spi_acpi_match[] = {
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{ "BRCM900D", 0 },
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{ "CAV900D", 0 },
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{ },
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};
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MODULE_DEVICE_TABLE(acpi, xlp_spi_acpi_match);
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#endif
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static struct platform_driver xlp_spi_driver = {
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.probe = xlp_spi_probe,
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.driver = {
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.name = "xlp-spi",
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.acpi_match_table = ACPI_PTR(xlp_spi_acpi_match),
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},
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};
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module_platform_driver(xlp_spi_driver);
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MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
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MODULE_DESCRIPTION("Netlogic XLP SPI controller driver");
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MODULE_LICENSE("GPL v2");
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