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7e963fb2a3
this patch add the support of ipm design. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220315032411.2826-4-leilk.liu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
1081 lines
28 KiB
C
1081 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Leilk Liu <leilk.liu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/gpio/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/spi-mt65xx.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/dma-mapping.h>
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#define SPI_CFG0_REG 0x0000
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#define SPI_CFG1_REG 0x0004
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#define SPI_TX_SRC_REG 0x0008
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#define SPI_RX_DST_REG 0x000c
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#define SPI_TX_DATA_REG 0x0010
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#define SPI_RX_DATA_REG 0x0014
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#define SPI_CMD_REG 0x0018
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#define SPI_STATUS0_REG 0x001c
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#define SPI_PAD_SEL_REG 0x0024
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#define SPI_CFG2_REG 0x0028
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#define SPI_TX_SRC_REG_64 0x002c
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#define SPI_RX_DST_REG_64 0x0030
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#define SPI_CFG3_IPM_REG 0x0040
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#define SPI_CFG0_SCK_HIGH_OFFSET 0
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#define SPI_CFG0_SCK_LOW_OFFSET 8
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#define SPI_CFG0_CS_HOLD_OFFSET 16
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#define SPI_CFG0_CS_SETUP_OFFSET 24
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#define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
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#define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
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#define SPI_CFG1_CS_IDLE_OFFSET 0
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#define SPI_CFG1_PACKET_LOOP_OFFSET 8
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#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
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#define SPI_CFG1_GET_TICK_DLY_OFFSET 29
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#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30
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#define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000
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#define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000
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#define SPI_CFG1_CS_IDLE_MASK 0xff
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#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
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#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
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#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
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#define SPI_CFG2_SCK_HIGH_OFFSET 0
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#define SPI_CFG2_SCK_LOW_OFFSET 16
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#define SPI_CMD_ACT BIT(0)
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#define SPI_CMD_RESUME BIT(1)
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#define SPI_CMD_RST BIT(2)
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#define SPI_CMD_PAUSE_EN BIT(4)
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#define SPI_CMD_DEASSERT BIT(5)
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#define SPI_CMD_SAMPLE_SEL BIT(6)
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#define SPI_CMD_CS_POL BIT(7)
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#define SPI_CMD_CPHA BIT(8)
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#define SPI_CMD_CPOL BIT(9)
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#define SPI_CMD_RX_DMA BIT(10)
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#define SPI_CMD_TX_DMA BIT(11)
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#define SPI_CMD_TXMSBF BIT(12)
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#define SPI_CMD_RXMSBF BIT(13)
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#define SPI_CMD_RX_ENDIAN BIT(14)
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#define SPI_CMD_TX_ENDIAN BIT(15)
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#define SPI_CMD_FINISH_IE BIT(16)
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#define SPI_CMD_PAUSE_IE BIT(17)
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#define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
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#define SPI_CMD_IPM_SPIM_LOOP BIT(21)
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#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
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#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)
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#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
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#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
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#define MT8173_SPI_MAX_PAD_SEL 3
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#define MTK_SPI_PAUSE_INT_STATUS 0x2
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#define MTK_SPI_IDLE 0
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#define MTK_SPI_PAUSED 1
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#define MTK_SPI_MAX_FIFO_SIZE 32U
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#define MTK_SPI_PACKET_SIZE 1024
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#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
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#define MTK_SPI_32BITS_MASK (0xffffffff)
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#define DMA_ADDR_EXT_BITS (36)
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#define DMA_ADDR_DEF_BITS (32)
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struct mtk_spi_compatible {
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bool need_pad_sel;
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/* Must explicitly send dummy Tx bytes to do Rx only transfer */
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bool must_tx;
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/* some IC design adjust cfg register to enhance time accuracy */
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bool enhance_timing;
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/* some IC support DMA addr extension */
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bool dma_ext;
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/* some IC no need unprepare SPI clk */
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bool no_need_unprepare;
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/* IPM design adjust and extend register to support more features */
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bool ipm_design;
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};
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struct mtk_spi {
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void __iomem *base;
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u32 state;
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int pad_num;
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u32 *pad_sel;
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struct clk *parent_clk, *sel_clk, *spi_clk;
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struct spi_transfer *cur_transfer;
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u32 xfer_len;
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u32 num_xfered;
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struct scatterlist *tx_sgl, *rx_sgl;
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u32 tx_sgl_len, rx_sgl_len;
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const struct mtk_spi_compatible *dev_comp;
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u32 spi_clk_hz;
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};
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static const struct mtk_spi_compatible mtk_common_compat;
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static const struct mtk_spi_compatible mt2712_compat = {
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.must_tx = true,
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};
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static const struct mtk_spi_compatible mtk_ipm_compat = {
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.enhance_timing = true,
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.dma_ext = true,
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.ipm_design = true,
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};
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static const struct mtk_spi_compatible mt6765_compat = {
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.need_pad_sel = true,
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.must_tx = true,
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.enhance_timing = true,
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.dma_ext = true,
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};
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static const struct mtk_spi_compatible mt7622_compat = {
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.must_tx = true,
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.enhance_timing = true,
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};
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static const struct mtk_spi_compatible mt8173_compat = {
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.need_pad_sel = true,
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.must_tx = true,
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};
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static const struct mtk_spi_compatible mt8183_compat = {
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.need_pad_sel = true,
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.must_tx = true,
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.enhance_timing = true,
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};
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static const struct mtk_spi_compatible mt6893_compat = {
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.need_pad_sel = true,
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.must_tx = true,
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.enhance_timing = true,
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.dma_ext = true,
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.no_need_unprepare = true,
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};
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/*
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* A piece of default chip info unless the platform
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* supplies it.
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*/
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static const struct mtk_chip_config mtk_default_chip_info = {
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.sample_sel = 0,
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.tick_delay = 0,
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};
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static const struct of_device_id mtk_spi_of_match[] = {
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{ .compatible = "mediatek,spi-ipm",
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.data = (void *)&mtk_ipm_compat,
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},
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{ .compatible = "mediatek,mt2701-spi",
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.data = (void *)&mtk_common_compat,
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},
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{ .compatible = "mediatek,mt2712-spi",
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.data = (void *)&mt2712_compat,
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},
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{ .compatible = "mediatek,mt6589-spi",
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.data = (void *)&mtk_common_compat,
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},
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{ .compatible = "mediatek,mt6765-spi",
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.data = (void *)&mt6765_compat,
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},
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{ .compatible = "mediatek,mt7622-spi",
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.data = (void *)&mt7622_compat,
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},
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{ .compatible = "mediatek,mt7629-spi",
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.data = (void *)&mt7622_compat,
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},
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{ .compatible = "mediatek,mt8135-spi",
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.data = (void *)&mtk_common_compat,
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},
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{ .compatible = "mediatek,mt8173-spi",
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.data = (void *)&mt8173_compat,
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},
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{ .compatible = "mediatek,mt8183-spi",
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.data = (void *)&mt8183_compat,
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},
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{ .compatible = "mediatek,mt8192-spi",
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.data = (void *)&mt6765_compat,
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},
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{ .compatible = "mediatek,mt6893-spi",
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.data = (void *)&mt6893_compat,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
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static void mtk_spi_reset(struct mtk_spi *mdata)
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{
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u32 reg_val;
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/* set the software reset bit in SPI_CMD_REG. */
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val |= SPI_CMD_RST;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val &= ~SPI_CMD_RST;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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}
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static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
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{
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struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
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struct spi_delay *cs_setup = &spi->cs_setup;
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struct spi_delay *cs_hold = &spi->cs_hold;
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struct spi_delay *cs_inactive = &spi->cs_inactive;
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u32 setup, hold, inactive;
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u32 reg_val;
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int delay;
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delay = spi_delay_to_ns(cs_setup, NULL);
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if (delay < 0)
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return delay;
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setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
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delay = spi_delay_to_ns(cs_hold, NULL);
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if (delay < 0)
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return delay;
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hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
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delay = spi_delay_to_ns(cs_inactive, NULL);
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if (delay < 0)
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return delay;
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inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
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if (hold || setup) {
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reg_val = readl(mdata->base + SPI_CFG0_REG);
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if (mdata->dev_comp->enhance_timing) {
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if (hold) {
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hold = min_t(u32, hold, 0x10000);
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reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
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reg_val |= (((hold - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
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}
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if (setup) {
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setup = min_t(u32, setup, 0x10000);
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reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
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reg_val |= (((setup - 1) & 0xffff)
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<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
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}
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} else {
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if (hold) {
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hold = min_t(u32, hold, 0x100);
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reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
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reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
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}
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if (setup) {
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setup = min_t(u32, setup, 0x100);
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reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
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reg_val |= (((setup - 1) & 0xff)
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<< SPI_CFG0_CS_SETUP_OFFSET);
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}
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}
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writel(reg_val, mdata->base + SPI_CFG0_REG);
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}
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if (inactive) {
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inactive = min_t(u32, inactive, 0x100);
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
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reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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return 0;
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}
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static int mtk_spi_hw_init(struct spi_master *master,
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struct spi_device *spi)
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{
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u16 cpha, cpol;
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u32 reg_val;
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struct mtk_chip_config *chip_config = spi->controller_data;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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cpha = spi->mode & SPI_CPHA ? 1 : 0;
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cpol = spi->mode & SPI_CPOL ? 1 : 0;
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reg_val = readl(mdata->base + SPI_CMD_REG);
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if (mdata->dev_comp->ipm_design) {
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/* SPI transfer without idle time until packet length done */
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reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
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if (spi->mode & SPI_LOOP)
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reg_val |= SPI_CMD_IPM_SPIM_LOOP;
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else
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reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
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}
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if (cpha)
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reg_val |= SPI_CMD_CPHA;
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else
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reg_val &= ~SPI_CMD_CPHA;
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if (cpol)
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reg_val |= SPI_CMD_CPOL;
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else
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reg_val &= ~SPI_CMD_CPOL;
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/* set the mlsbx and mlsbtx */
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if (spi->mode & SPI_LSB_FIRST) {
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reg_val &= ~SPI_CMD_TXMSBF;
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reg_val &= ~SPI_CMD_RXMSBF;
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} else {
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reg_val |= SPI_CMD_TXMSBF;
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reg_val |= SPI_CMD_RXMSBF;
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}
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/* set the tx/rx endian */
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#ifdef __LITTLE_ENDIAN
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reg_val &= ~SPI_CMD_TX_ENDIAN;
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reg_val &= ~SPI_CMD_RX_ENDIAN;
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#else
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reg_val |= SPI_CMD_TX_ENDIAN;
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reg_val |= SPI_CMD_RX_ENDIAN;
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#endif
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if (mdata->dev_comp->enhance_timing) {
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/* set CS polarity */
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if (spi->mode & SPI_CS_HIGH)
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reg_val |= SPI_CMD_CS_POL;
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else
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reg_val &= ~SPI_CMD_CS_POL;
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if (chip_config->sample_sel)
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reg_val |= SPI_CMD_SAMPLE_SEL;
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else
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reg_val &= ~SPI_CMD_SAMPLE_SEL;
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}
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/* set finish and pause interrupt always enable */
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reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
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/* disable dma mode */
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reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
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/* disable deassert mode */
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reg_val &= ~SPI_CMD_DEASSERT;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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/* pad select */
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if (mdata->dev_comp->need_pad_sel)
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writel(mdata->pad_sel[spi->chip_select],
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mdata->base + SPI_PAD_SEL_REG);
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/* tick delay */
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if (mdata->dev_comp->enhance_timing) {
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if (mdata->dev_comp->ipm_design) {
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
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reg_val |= ((chip_config->tick_delay & 0x7)
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<< SPI_CMD_IPM_GET_TICKDLY_OFFSET);
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writel(reg_val, mdata->base + SPI_CMD_REG);
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} else {
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
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reg_val |= ((chip_config->tick_delay & 0x7)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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} else {
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
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reg_val |= ((chip_config->tick_delay & 0x3)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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/* set hw cs timing */
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mtk_spi_set_hw_cs_timing(spi);
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return 0;
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}
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static int mtk_spi_prepare_message(struct spi_master *master,
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struct spi_message *msg)
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{
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return mtk_spi_hw_init(master, msg->spi);
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}
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static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
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{
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u32 reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
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if (spi->mode & SPI_CS_HIGH)
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enable = !enable;
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reg_val = readl(mdata->base + SPI_CMD_REG);
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if (!enable) {
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reg_val |= SPI_CMD_PAUSE_EN;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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} else {
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reg_val &= ~SPI_CMD_PAUSE_EN;
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writel(reg_val, mdata->base + SPI_CMD_REG);
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mdata->state = MTK_SPI_IDLE;
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mtk_spi_reset(mdata);
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}
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}
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static void mtk_spi_prepare_transfer(struct spi_master *master,
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u32 speed_hz)
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{
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u32 div, sck_time, reg_val;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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if (speed_hz < mdata->spi_clk_hz / 2)
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div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
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else
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div = 1;
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sck_time = (div + 1) / 2;
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if (mdata->dev_comp->enhance_timing) {
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reg_val = readl(mdata->base + SPI_CFG2_REG);
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reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
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reg_val |= (((sck_time - 1) & 0xffff)
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<< SPI_CFG2_SCK_HIGH_OFFSET);
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reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
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reg_val |= (((sck_time - 1) & 0xffff)
|
|
<< SPI_CFG2_SCK_LOW_OFFSET);
|
|
writel(reg_val, mdata->base + SPI_CFG2_REG);
|
|
} else {
|
|
reg_val = readl(mdata->base + SPI_CFG0_REG);
|
|
reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
|
|
reg_val |= (((sck_time - 1) & 0xff)
|
|
<< SPI_CFG0_SCK_HIGH_OFFSET);
|
|
reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
|
|
reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
|
|
writel(reg_val, mdata->base + SPI_CFG0_REG);
|
|
}
|
|
}
|
|
|
|
static void mtk_spi_setup_packet(struct spi_master *master)
|
|
{
|
|
u32 packet_size, packet_loop, reg_val;
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
if (mdata->dev_comp->ipm_design)
|
|
packet_size = min_t(u32,
|
|
mdata->xfer_len,
|
|
MTK_SPI_IPM_PACKET_SIZE);
|
|
else
|
|
packet_size = min_t(u32,
|
|
mdata->xfer_len,
|
|
MTK_SPI_PACKET_SIZE);
|
|
|
|
packet_loop = mdata->xfer_len / packet_size;
|
|
|
|
reg_val = readl(mdata->base + SPI_CFG1_REG);
|
|
if (mdata->dev_comp->ipm_design)
|
|
reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
|
|
else
|
|
reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
|
|
reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
|
|
reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
|
|
reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
|
|
writel(reg_val, mdata->base + SPI_CFG1_REG);
|
|
}
|
|
|
|
static void mtk_spi_enable_transfer(struct spi_master *master)
|
|
{
|
|
u32 cmd;
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
cmd = readl(mdata->base + SPI_CMD_REG);
|
|
if (mdata->state == MTK_SPI_IDLE)
|
|
cmd |= SPI_CMD_ACT;
|
|
else
|
|
cmd |= SPI_CMD_RESUME;
|
|
writel(cmd, mdata->base + SPI_CMD_REG);
|
|
}
|
|
|
|
static int mtk_spi_get_mult_delta(u32 xfer_len)
|
|
{
|
|
u32 mult_delta;
|
|
|
|
if (xfer_len > MTK_SPI_PACKET_SIZE)
|
|
mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
|
|
else
|
|
mult_delta = 0;
|
|
|
|
return mult_delta;
|
|
}
|
|
|
|
static void mtk_spi_update_mdata_len(struct spi_master *master)
|
|
{
|
|
int mult_delta;
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
|
|
if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
|
|
mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
|
|
mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
|
|
mdata->rx_sgl_len = mult_delta;
|
|
mdata->tx_sgl_len -= mdata->xfer_len;
|
|
} else {
|
|
mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
|
|
mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
|
|
mdata->tx_sgl_len = mult_delta;
|
|
mdata->rx_sgl_len -= mdata->xfer_len;
|
|
}
|
|
} else if (mdata->tx_sgl_len) {
|
|
mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
|
|
mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
|
|
mdata->tx_sgl_len = mult_delta;
|
|
} else if (mdata->rx_sgl_len) {
|
|
mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
|
|
mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
|
|
mdata->rx_sgl_len = mult_delta;
|
|
}
|
|
}
|
|
|
|
static void mtk_spi_setup_dma_addr(struct spi_master *master,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
if (mdata->tx_sgl) {
|
|
writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
|
|
mdata->base + SPI_TX_SRC_REG);
|
|
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
|
if (mdata->dev_comp->dma_ext)
|
|
writel((u32)(xfer->tx_dma >> 32),
|
|
mdata->base + SPI_TX_SRC_REG_64);
|
|
#endif
|
|
}
|
|
|
|
if (mdata->rx_sgl) {
|
|
writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
|
|
mdata->base + SPI_RX_DST_REG);
|
|
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
|
if (mdata->dev_comp->dma_ext)
|
|
writel((u32)(xfer->rx_dma >> 32),
|
|
mdata->base + SPI_RX_DST_REG_64);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static int mtk_spi_fifo_transfer(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
int cnt, remainder;
|
|
u32 reg_val;
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
mdata->cur_transfer = xfer;
|
|
mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
|
|
mdata->num_xfered = 0;
|
|
mtk_spi_prepare_transfer(master, xfer->speed_hz);
|
|
mtk_spi_setup_packet(master);
|
|
|
|
if (xfer->tx_buf) {
|
|
cnt = xfer->len / 4;
|
|
iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
|
|
remainder = xfer->len % 4;
|
|
if (remainder > 0) {
|
|
reg_val = 0;
|
|
memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
|
|
writel(reg_val, mdata->base + SPI_TX_DATA_REG);
|
|
}
|
|
}
|
|
|
|
mtk_spi_enable_transfer(master);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int mtk_spi_dma_transfer(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
int cmd;
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
mdata->tx_sgl = NULL;
|
|
mdata->rx_sgl = NULL;
|
|
mdata->tx_sgl_len = 0;
|
|
mdata->rx_sgl_len = 0;
|
|
mdata->cur_transfer = xfer;
|
|
mdata->num_xfered = 0;
|
|
|
|
mtk_spi_prepare_transfer(master, xfer->speed_hz);
|
|
|
|
cmd = readl(mdata->base + SPI_CMD_REG);
|
|
if (xfer->tx_buf)
|
|
cmd |= SPI_CMD_TX_DMA;
|
|
if (xfer->rx_buf)
|
|
cmd |= SPI_CMD_RX_DMA;
|
|
writel(cmd, mdata->base + SPI_CMD_REG);
|
|
|
|
if (xfer->tx_buf)
|
|
mdata->tx_sgl = xfer->tx_sg.sgl;
|
|
if (xfer->rx_buf)
|
|
mdata->rx_sgl = xfer->rx_sg.sgl;
|
|
|
|
if (mdata->tx_sgl) {
|
|
xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
|
|
mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
|
|
}
|
|
if (mdata->rx_sgl) {
|
|
xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
|
|
mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
|
|
}
|
|
|
|
mtk_spi_update_mdata_len(master);
|
|
mtk_spi_setup_packet(master);
|
|
mtk_spi_setup_dma_addr(master, xfer);
|
|
mtk_spi_enable_transfer(master);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int mtk_spi_transfer_one(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
|
|
u32 reg_val = 0;
|
|
|
|
/* prepare xfer direction and duplex mode */
|
|
if (mdata->dev_comp->ipm_design) {
|
|
if (!xfer->tx_buf || !xfer->rx_buf) {
|
|
reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
|
|
if (xfer->rx_buf)
|
|
reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
|
|
}
|
|
writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
|
|
}
|
|
|
|
if (master->can_dma(master, spi, xfer))
|
|
return mtk_spi_dma_transfer(master, spi, xfer);
|
|
else
|
|
return mtk_spi_fifo_transfer(master, spi, xfer);
|
|
}
|
|
|
|
static bool mtk_spi_can_dma(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
/* Buffers for DMA transactions must be 4-byte aligned */
|
|
return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
|
|
(unsigned long)xfer->tx_buf % 4 == 0 &&
|
|
(unsigned long)xfer->rx_buf % 4 == 0);
|
|
}
|
|
|
|
static int mtk_spi_setup(struct spi_device *spi)
|
|
{
|
|
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
|
|
|
|
if (!spi->controller_data)
|
|
spi->controller_data = (void *)&mtk_default_chip_info;
|
|
|
|
if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
|
|
/* CS de-asserted, gpiolib will handle inversion */
|
|
gpiod_direction_output(spi->cs_gpiod, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
|
|
{
|
|
u32 cmd, reg_val, cnt, remainder, len;
|
|
struct spi_master *master = dev_id;
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
struct spi_transfer *trans = mdata->cur_transfer;
|
|
|
|
reg_val = readl(mdata->base + SPI_STATUS0_REG);
|
|
if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
|
|
mdata->state = MTK_SPI_PAUSED;
|
|
else
|
|
mdata->state = MTK_SPI_IDLE;
|
|
|
|
if (!master->can_dma(master, NULL, trans)) {
|
|
if (trans->rx_buf) {
|
|
cnt = mdata->xfer_len / 4;
|
|
ioread32_rep(mdata->base + SPI_RX_DATA_REG,
|
|
trans->rx_buf + mdata->num_xfered, cnt);
|
|
remainder = mdata->xfer_len % 4;
|
|
if (remainder > 0) {
|
|
reg_val = readl(mdata->base + SPI_RX_DATA_REG);
|
|
memcpy(trans->rx_buf +
|
|
mdata->num_xfered +
|
|
(cnt * 4),
|
|
®_val,
|
|
remainder);
|
|
}
|
|
}
|
|
|
|
mdata->num_xfered += mdata->xfer_len;
|
|
if (mdata->num_xfered == trans->len) {
|
|
spi_finalize_current_transfer(master);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
len = trans->len - mdata->num_xfered;
|
|
mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
|
|
mtk_spi_setup_packet(master);
|
|
|
|
cnt = mdata->xfer_len / 4;
|
|
iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
|
|
trans->tx_buf + mdata->num_xfered, cnt);
|
|
|
|
remainder = mdata->xfer_len % 4;
|
|
if (remainder > 0) {
|
|
reg_val = 0;
|
|
memcpy(®_val,
|
|
trans->tx_buf + (cnt * 4) + mdata->num_xfered,
|
|
remainder);
|
|
writel(reg_val, mdata->base + SPI_TX_DATA_REG);
|
|
}
|
|
|
|
mtk_spi_enable_transfer(master);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
if (mdata->tx_sgl)
|
|
trans->tx_dma += mdata->xfer_len;
|
|
if (mdata->rx_sgl)
|
|
trans->rx_dma += mdata->xfer_len;
|
|
|
|
if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
|
|
mdata->tx_sgl = sg_next(mdata->tx_sgl);
|
|
if (mdata->tx_sgl) {
|
|
trans->tx_dma = sg_dma_address(mdata->tx_sgl);
|
|
mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
|
|
}
|
|
}
|
|
if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
|
|
mdata->rx_sgl = sg_next(mdata->rx_sgl);
|
|
if (mdata->rx_sgl) {
|
|
trans->rx_dma = sg_dma_address(mdata->rx_sgl);
|
|
mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
|
|
}
|
|
}
|
|
|
|
if (!mdata->tx_sgl && !mdata->rx_sgl) {
|
|
/* spi disable dma */
|
|
cmd = readl(mdata->base + SPI_CMD_REG);
|
|
cmd &= ~SPI_CMD_TX_DMA;
|
|
cmd &= ~SPI_CMD_RX_DMA;
|
|
writel(cmd, mdata->base + SPI_CMD_REG);
|
|
|
|
spi_finalize_current_transfer(master);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
mtk_spi_update_mdata_len(master);
|
|
mtk_spi_setup_packet(master);
|
|
mtk_spi_setup_dma_addr(master, trans);
|
|
mtk_spi_enable_transfer(master);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int mtk_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct mtk_spi *mdata;
|
|
const struct of_device_id *of_id;
|
|
int i, irq, ret, addr_bits;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
|
|
if (!master) {
|
|
dev_err(&pdev->dev, "failed to alloc spi master\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
master->auto_runtime_pm = true;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
|
|
|
|
master->set_cs = mtk_spi_set_cs;
|
|
master->prepare_message = mtk_spi_prepare_message;
|
|
master->transfer_one = mtk_spi_transfer_one;
|
|
master->can_dma = mtk_spi_can_dma;
|
|
master->setup = mtk_spi_setup;
|
|
master->set_cs_timing = mtk_spi_set_hw_cs_timing;
|
|
master->use_gpio_descriptors = true;
|
|
|
|
of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
|
|
if (!of_id) {
|
|
dev_err(&pdev->dev, "failed to probe of_node\n");
|
|
ret = -EINVAL;
|
|
goto err_put_master;
|
|
}
|
|
|
|
mdata = spi_master_get_devdata(master);
|
|
mdata->dev_comp = of_id->data;
|
|
|
|
if (mdata->dev_comp->enhance_timing)
|
|
master->mode_bits |= SPI_CS_HIGH;
|
|
|
|
if (mdata->dev_comp->must_tx)
|
|
master->flags = SPI_MASTER_MUST_TX;
|
|
if (mdata->dev_comp->ipm_design)
|
|
master->mode_bits |= SPI_LOOP;
|
|
|
|
if (mdata->dev_comp->need_pad_sel) {
|
|
mdata->pad_num = of_property_count_u32_elems(
|
|
pdev->dev.of_node,
|
|
"mediatek,pad-select");
|
|
if (mdata->pad_num < 0) {
|
|
dev_err(&pdev->dev,
|
|
"No 'mediatek,pad-select' property\n");
|
|
ret = -EINVAL;
|
|
goto err_put_master;
|
|
}
|
|
|
|
mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num,
|
|
sizeof(u32), GFP_KERNEL);
|
|
if (!mdata->pad_sel) {
|
|
ret = -ENOMEM;
|
|
goto err_put_master;
|
|
}
|
|
|
|
for (i = 0; i < mdata->pad_num; i++) {
|
|
of_property_read_u32_index(pdev->dev.of_node,
|
|
"mediatek,pad-select",
|
|
i, &mdata->pad_sel[i]);
|
|
if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) {
|
|
dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n",
|
|
i, mdata->pad_sel[i]);
|
|
ret = -EINVAL;
|
|
goto err_put_master;
|
|
}
|
|
}
|
|
}
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
mdata->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(mdata->base)) {
|
|
ret = PTR_ERR(mdata->base);
|
|
goto err_put_master;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
ret = irq;
|
|
goto err_put_master;
|
|
}
|
|
|
|
if (!pdev->dev.dma_mask)
|
|
pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
|
|
IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
|
|
goto err_put_master;
|
|
}
|
|
|
|
mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
|
|
if (IS_ERR(mdata->parent_clk)) {
|
|
ret = PTR_ERR(mdata->parent_clk);
|
|
dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
|
|
goto err_put_master;
|
|
}
|
|
|
|
mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
|
|
if (IS_ERR(mdata->sel_clk)) {
|
|
ret = PTR_ERR(mdata->sel_clk);
|
|
dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret);
|
|
goto err_put_master;
|
|
}
|
|
|
|
mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
|
|
if (IS_ERR(mdata->spi_clk)) {
|
|
ret = PTR_ERR(mdata->spi_clk);
|
|
dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
|
|
goto err_put_master;
|
|
}
|
|
|
|
ret = clk_prepare_enable(mdata->spi_clk);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
|
|
goto err_put_master;
|
|
}
|
|
|
|
ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
goto err_put_master;
|
|
}
|
|
|
|
mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
|
|
|
|
if (mdata->dev_comp->no_need_unprepare)
|
|
clk_disable(mdata->spi_clk);
|
|
else
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
if (mdata->dev_comp->need_pad_sel) {
|
|
if (mdata->pad_num != master->num_chipselect) {
|
|
dev_err(&pdev->dev,
|
|
"pad_num does not match num_chipselect(%d != %d)\n",
|
|
mdata->pad_num, master->num_chipselect);
|
|
ret = -EINVAL;
|
|
goto err_disable_runtime_pm;
|
|
}
|
|
|
|
if (!master->cs_gpiods && master->num_chipselect > 1) {
|
|
dev_err(&pdev->dev,
|
|
"cs_gpios not specified and num_chipselect > 1\n");
|
|
ret = -EINVAL;
|
|
goto err_disable_runtime_pm;
|
|
}
|
|
}
|
|
|
|
if (mdata->dev_comp->dma_ext)
|
|
addr_bits = DMA_ADDR_EXT_BITS;
|
|
else
|
|
addr_bits = DMA_ADDR_DEF_BITS;
|
|
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
|
|
if (ret)
|
|
dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
|
|
addr_bits, ret);
|
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
|
|
goto err_disable_runtime_pm;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_disable_runtime_pm:
|
|
pm_runtime_disable(&pdev->dev);
|
|
err_put_master:
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
mtk_spi_reset(mdata);
|
|
|
|
if (mdata->dev_comp->no_need_unprepare)
|
|
clk_unprepare(mdata->spi_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int mtk_spi_suspend(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
ret = spi_master_suspend(master);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!pm_runtime_suspended(dev))
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_spi_resume(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
if (!pm_runtime_suspended(dev)) {
|
|
ret = clk_prepare_enable(mdata->spi_clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
ret = spi_master_resume(master);
|
|
if (ret < 0)
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
#ifdef CONFIG_PM
|
|
static int mtk_spi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
if (mdata->dev_comp->no_need_unprepare)
|
|
clk_disable(mdata->spi_clk);
|
|
else
|
|
clk_disable_unprepare(mdata->spi_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_spi_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
if (mdata->dev_comp->no_need_unprepare)
|
|
ret = clk_enable(mdata->spi_clk);
|
|
else
|
|
ret = clk_prepare_enable(mdata->spi_clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
static const struct dev_pm_ops mtk_spi_pm = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
|
|
SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
|
|
mtk_spi_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver mtk_spi_driver = {
|
|
.driver = {
|
|
.name = "mtk-spi",
|
|
.pm = &mtk_spi_pm,
|
|
.of_match_table = mtk_spi_of_match,
|
|
},
|
|
.probe = mtk_spi_probe,
|
|
.remove = mtk_spi_remove,
|
|
};
|
|
|
|
module_platform_driver(mtk_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("MTK SPI Controller driver");
|
|
MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:mtk-spi");
|