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8d37f2710f
My patch created compilation bugs in the MPC512x-PSC driver.
Fix them up.
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: linuxppc-dev@lists.ozlabs.org
Reported-by: kernel test robot <lkp@intel.com>
Fixes: 2818824ced
(" spi: mpc512x-psc: Convert to use GPIO descriptors")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220201234535.569973-1-linus.walleij@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
617 lines
16 KiB
C
617 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC512x PSC in SPI mode driver.
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*
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* Copyright (C) 2007,2008 Freescale Semiconductor Inc.
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* Original port from 52xx driver:
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* Hongjun Chen <hong-jun.chen@freescale.com>
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*
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* Fork of mpc52xx_psc_spi.c:
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* Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/completion.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/spi/spi.h>
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#include <linux/fsl_devices.h>
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#include <asm/mpc52xx_psc.h>
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enum {
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TYPE_MPC5121,
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TYPE_MPC5125,
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};
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/*
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* This macro abstracts the differences in the PSC register layout between
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* MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
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*/
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#define psc_addr(mps, regname) ({ \
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void *__ret = NULL; \
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switch (mps->type) { \
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case TYPE_MPC5121: { \
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struct mpc52xx_psc __iomem *psc = mps->psc; \
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__ret = &psc->regname; \
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}; \
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break; \
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case TYPE_MPC5125: { \
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struct mpc5125_psc __iomem *psc = mps->psc; \
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__ret = &psc->regname; \
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}; \
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break; \
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} \
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__ret; })
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struct mpc512x_psc_spi {
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void (*cs_control)(struct spi_device *spi, bool on);
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/* driver internal data */
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int type;
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void __iomem *psc;
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struct mpc512x_psc_fifo __iomem *fifo;
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unsigned int irq;
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u8 bits_per_word;
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struct clk *clk_mclk;
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struct clk *clk_ipg;
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u32 mclk_rate;
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struct completion txisrdone;
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};
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/* controller state */
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struct mpc512x_psc_spi_cs {
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int bits_per_word;
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int speed_hz;
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};
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/* set clock freq, clock ramp, bits per work
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* if t is NULL then reset the values to the default values
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*/
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static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc512x_psc_spi_cs *cs = spi->controller_state;
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cs->speed_hz = (t && t->speed_hz)
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? t->speed_hz : spi->max_speed_hz;
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cs->bits_per_word = (t && t->bits_per_word)
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? t->bits_per_word : spi->bits_per_word;
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cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
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return 0;
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}
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static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
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{
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struct mpc512x_psc_spi_cs *cs = spi->controller_state;
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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u32 sicr;
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u32 ccr;
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int speed;
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u16 bclkdiv;
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sicr = in_be32(psc_addr(mps, sicr));
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/* Set clock phase and polarity */
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if (spi->mode & SPI_CPHA)
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sicr |= 0x00001000;
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else
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sicr &= ~0x00001000;
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if (spi->mode & SPI_CPOL)
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sicr |= 0x00002000;
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else
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sicr &= ~0x00002000;
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if (spi->mode & SPI_LSB_FIRST)
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sicr |= 0x10000000;
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else
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sicr &= ~0x10000000;
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out_be32(psc_addr(mps, sicr), sicr);
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ccr = in_be32(psc_addr(mps, ccr));
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ccr &= 0xFF000000;
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speed = cs->speed_hz;
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if (!speed)
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speed = 1000000; /* default 1MHz */
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bclkdiv = (mps->mclk_rate / speed) - 1;
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ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
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out_be32(psc_addr(mps, ccr), ccr);
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mps->bits_per_word = cs->bits_per_word;
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if (spi->cs_gpiod) {
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if (mps->cs_control)
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/* boardfile override */
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mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
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else
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/* gpiolib will deal with the inversion */
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gpiod_set_value(spi->cs_gpiod, 1);
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}
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}
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static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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if (spi->cs_gpiod) {
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if (mps->cs_control)
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/* boardfile override */
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mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
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else
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/* gpiolib will deal with the inversion */
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gpiod_set_value(spi->cs_gpiod, 0);
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}
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}
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/* extract and scale size field in txsz or rxsz */
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#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
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#define EOFBYTE 1
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static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
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struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
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size_t tx_len = t->len;
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size_t rx_len = t->len;
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u8 *tx_buf = (u8 *)t->tx_buf;
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u8 *rx_buf = (u8 *)t->rx_buf;
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if (!tx_buf && !rx_buf && t->len)
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return -EINVAL;
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while (rx_len || tx_len) {
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size_t txcount;
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u8 data;
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size_t fifosz;
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size_t rxcount;
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int rxtries;
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/*
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* send the TX bytes in as large a chunk as possible
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* but neither exceed the TX nor the RX FIFOs
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*/
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fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
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txcount = min(fifosz, tx_len);
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fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
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fifosz -= in_be32(&fifo->rxcnt) + 1;
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txcount = min(fifosz, txcount);
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if (txcount) {
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/* fill the TX FIFO */
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while (txcount-- > 0) {
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data = tx_buf ? *tx_buf++ : 0;
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if (tx_len == EOFBYTE && t->cs_change)
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setbits32(&fifo->txcmd,
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MPC512x_PSC_FIFO_EOF);
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out_8(&fifo->txdata_8, data);
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tx_len--;
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}
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/* have the ISR trigger when the TX FIFO is empty */
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reinit_completion(&mps->txisrdone);
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out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
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out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
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wait_for_completion(&mps->txisrdone);
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}
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/*
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* consume as much RX data as the FIFO holds, while we
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* iterate over the transfer's TX data length
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*
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* only insist in draining all the remaining RX bytes
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* when the TX bytes were exhausted (that's at the very
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* end of this transfer, not when still iterating over
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* the transfer's chunks)
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*/
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rxtries = 50;
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do {
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/*
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* grab whatever was in the FIFO when we started
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* looking, don't bother fetching what was added to
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* the FIFO while we read from it -- we'll return
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* here eventually and prefer sending out remaining
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* TX data
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*/
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fifosz = in_be32(&fifo->rxcnt);
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rxcount = min(fifosz, rx_len);
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while (rxcount-- > 0) {
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data = in_8(&fifo->rxdata_8);
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if (rx_buf)
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*rx_buf++ = data;
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rx_len--;
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}
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/*
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* come back later if there still is TX data to send,
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* bail out of the RX drain loop if all of the TX data
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* was sent and all of the RX data was received (i.e.
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* when the transmission has completed)
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*/
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if (tx_len)
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break;
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if (!rx_len)
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break;
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/*
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* TX data transmission has completed while RX data
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* is still pending -- that's a transient situation
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* which depends on wire speed and specific
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* hardware implementation details (buffering) yet
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* should resolve very quickly
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*
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* just yield for a moment to not hog the CPU for
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* too long when running SPI at low speed
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*
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* the timeout range is rather arbitrary and tries
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* to balance throughput against system load; the
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* chosen values result in a minimal timeout of 50
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* times 10us and thus work at speeds as low as
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* some 20kbps, while the maximum timeout at the
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* transfer's end could be 5ms _if_ nothing else
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* ticks in the system _and_ RX data still wasn't
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* received, which only occurs in situations that
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* are exceptional; removing the unpredictability
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* of the timeout either decreases throughput
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* (longer timeouts), or puts more load on the
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* system (fixed short timeouts) or requires the
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* use of a timeout API instead of a counter and an
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* unknown inner delay
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*/
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usleep_range(10, 100);
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} while (--rxtries > 0);
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if (!tx_len && rx_len && !rxtries) {
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/*
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* not enough RX bytes even after several retries
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* and the resulting rather long timeout?
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*/
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rxcount = in_be32(&fifo->rxcnt);
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dev_warn(&spi->dev,
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"short xfer, missing %zd RX bytes, FIFO level %zd\n",
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rx_len, rxcount);
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}
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/*
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* drain and drop RX data which "should not be there" in
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* the first place, for undisturbed transmission this turns
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* into a NOP (except for the FIFO level fetch)
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*/
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if (!tx_len && !rx_len) {
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while (in_be32(&fifo->rxcnt))
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in_8(&fifo->rxdata_8);
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}
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}
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return 0;
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}
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static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
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struct spi_message *m)
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{
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struct spi_device *spi;
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unsigned cs_change;
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int status;
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struct spi_transfer *t;
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spi = m->spi;
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cs_change = 1;
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status = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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status = mpc512x_psc_spi_transfer_setup(spi, t);
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if (status < 0)
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break;
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if (cs_change)
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mpc512x_psc_spi_activate_cs(spi);
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cs_change = t->cs_change;
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status = mpc512x_psc_spi_transfer_rxtx(spi, t);
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if (status)
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break;
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m->actual_length += t->len;
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spi_transfer_delay_exec(t);
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if (cs_change)
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mpc512x_psc_spi_deactivate_cs(spi);
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}
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m->status = status;
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if (m->complete)
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m->complete(m->context);
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if (status || !cs_change)
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mpc512x_psc_spi_deactivate_cs(spi);
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mpc512x_psc_spi_transfer_setup(spi, NULL);
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spi_finalize_current_message(master);
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return status;
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}
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static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
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dev_dbg(&master->dev, "%s()\n", __func__);
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/* Zero MR2 */
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in_8(psc_addr(mps, mr2));
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out_8(psc_addr(mps, mr2), 0x0);
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/* enable transmitter/receiver */
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out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
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return 0;
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}
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static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
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{
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
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struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
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dev_dbg(&master->dev, "%s()\n", __func__);
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/* disable transmitter/receiver and fifo interrupt */
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out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
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out_be32(&fifo->tximr, 0);
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return 0;
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}
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static int mpc512x_psc_spi_setup(struct spi_device *spi)
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{
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struct mpc512x_psc_spi_cs *cs = spi->controller_state;
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if (spi->bits_per_word % 8)
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return -EINVAL;
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if (!cs) {
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cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi->controller_state = cs;
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}
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cs->bits_per_word = spi->bits_per_word;
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cs->speed_hz = spi->max_speed_hz;
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return 0;
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}
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static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
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{
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kfree(spi->controller_state);
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}
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static int mpc512x_psc_spi_port_config(struct spi_master *master,
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struct mpc512x_psc_spi *mps)
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{
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struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
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u32 sicr;
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u32 ccr;
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int speed;
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u16 bclkdiv;
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/* Reset the PSC into a known state */
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out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
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out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
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out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
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/* Disable psc interrupts all useful interrupts are in fifo */
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out_be16(psc_addr(mps, isr_imr.imr), 0);
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/* Disable fifo interrupts, will be enabled later */
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out_be32(&fifo->tximr, 0);
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out_be32(&fifo->rximr, 0);
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/* Setup fifo slice address and size */
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/*out_be32(&fifo->txsz, 0x0fe00004);*/
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/*out_be32(&fifo->rxsz, 0x0ff00004);*/
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sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
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0x00800000 | /* GenClk = 1 -- internal clk */
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0x00008000 | /* SPI = 1 */
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0x00004000 | /* MSTR = 1 -- SPI master */
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0x00000800; /* UseEOF = 1 -- SS low until EOF */
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out_be32(psc_addr(mps, sicr), sicr);
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ccr = in_be32(psc_addr(mps, ccr));
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ccr &= 0xFF000000;
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speed = 1000000; /* default 1MHz */
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bclkdiv = (mps->mclk_rate / speed) - 1;
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ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
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out_be32(psc_addr(mps, ccr), ccr);
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/* Set 2ms DTL delay */
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out_8(psc_addr(mps, ctur), 0x00);
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out_8(psc_addr(mps, ctlr), 0x82);
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/* we don't use the alarms */
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out_be32(&fifo->rxalarm, 0xfff);
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out_be32(&fifo->txalarm, 0);
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/* Enable FIFO slices for Rx/Tx */
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out_be32(&fifo->rxcmd,
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MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
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out_be32(&fifo->txcmd,
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MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
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mps->bits_per_word = 8;
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return 0;
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}
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static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
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{
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struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
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struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
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/* clear interrupt and wake up the rx/tx routine */
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if (in_be32(&fifo->txisr) &
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in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
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out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
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out_be32(&fifo->tximr, 0);
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complete(&mps->txisrdone);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
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u32 size, unsigned int irq)
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{
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struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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struct mpc512x_psc_spi *mps;
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struct spi_master *master;
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int ret;
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void *tempp;
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struct clk *clk;
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master = spi_alloc_master(dev, sizeof(*mps));
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if (master == NULL)
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return -ENOMEM;
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dev_set_drvdata(dev, master);
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mps = spi_master_get_devdata(master);
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mps->type = (int)of_device_get_match_data(dev);
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mps->irq = irq;
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if (pdata) {
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mps->cs_control = pdata->cs_control;
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->max_chipselect;
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}
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
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master->setup = mpc512x_psc_spi_setup;
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master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
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master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
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master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
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master->use_gpio_descriptors = true;
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master->cleanup = mpc512x_psc_spi_cleanup;
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master->dev.of_node = dev->of_node;
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tempp = devm_ioremap(dev, regaddr, size);
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if (!tempp) {
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dev_err(dev, "could not ioremap I/O port range\n");
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ret = -EFAULT;
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goto free_master;
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}
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mps->psc = tempp;
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mps->fifo =
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(struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
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ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
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"mpc512x-psc-spi", mps);
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if (ret)
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goto free_master;
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init_completion(&mps->txisrdone);
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clk = devm_clk_get(dev, "mclk");
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto free_master;
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}
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ret = clk_prepare_enable(clk);
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if (ret)
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goto free_master;
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mps->clk_mclk = clk;
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mps->mclk_rate = clk_get_rate(clk);
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clk = devm_clk_get(dev, "ipg");
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto free_mclk_clock;
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}
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ret = clk_prepare_enable(clk);
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if (ret)
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goto free_mclk_clock;
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mps->clk_ipg = clk;
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ret = mpc512x_psc_spi_port_config(master, mps);
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if (ret < 0)
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goto free_ipg_clock;
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ret = devm_spi_register_master(dev, master);
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if (ret < 0)
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goto free_ipg_clock;
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return ret;
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free_ipg_clock:
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clk_disable_unprepare(mps->clk_ipg);
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free_mclk_clock:
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clk_disable_unprepare(mps->clk_mclk);
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free_master:
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spi_master_put(master);
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return ret;
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}
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static int mpc512x_psc_spi_do_remove(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
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clk_disable_unprepare(mps->clk_mclk);
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clk_disable_unprepare(mps->clk_ipg);
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return 0;
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}
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static int mpc512x_psc_spi_of_probe(struct platform_device *op)
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{
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const u32 *regaddr_p;
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u64 regaddr64, size64;
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regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
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if (!regaddr_p) {
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dev_err(&op->dev, "Invalid PSC address\n");
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return -EINVAL;
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}
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regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
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return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
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irq_of_parse_and_map(op->dev.of_node, 0));
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}
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static int mpc512x_psc_spi_of_remove(struct platform_device *op)
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{
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return mpc512x_psc_spi_do_remove(&op->dev);
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}
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static const struct of_device_id mpc512x_psc_spi_of_match[] = {
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{ .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
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{ .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
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{},
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};
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MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
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static struct platform_driver mpc512x_psc_spi_of_driver = {
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.probe = mpc512x_psc_spi_of_probe,
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.remove = mpc512x_psc_spi_of_remove,
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.driver = {
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.name = "mpc512x-psc-spi",
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.of_match_table = mpc512x_psc_spi_of_match,
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},
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};
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module_platform_driver(mpc512x_psc_spi_of_driver);
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MODULE_AUTHOR("John Rigby");
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MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
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MODULE_LICENSE("GPL");
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