mirror of
https://github.com/torvalds/linux.git
synced 2024-12-09 04:31:39 +00:00
e35a4a4e13
* Replace the expert mode symbols with a single helper * Fix misuses of of_match_ptr() * Remove partid and partname debugfs files * tests: Fix eraseblock read speed miscalculation for lower partition sizes * TRX parser: Allow to use on MediaTek MIPS SoCs MTD driver changes: * spear_smi: use GFP_KERNEL * mchp48l640: Add SPI ID table * mchp23k256: Add SPI ID table * blkdevs: Avoid soft lockups with some mtd/spi devices * aspeed-smc: Improve probe resilience Hyperbus changes: * HBMC_AM654 should depend on ARCH_K3 NAND core changes: * ECC: - Add infrastructure to support hardware engines - Add a new helper to retrieve the ECC context - Provide a helper to retrieve a pilelined engine device NAND-ECC changes: * Macronix ECC engine: - Add Macronix external ECC engine support - Support SPI pipelined mode - Make two read-only arrays static const - Fix compile test issue Raw NAND core changes: * Fix misuses of of_match_node() * Rework of_get_nand_bus_width() * Remove of_get_nand_on_flash_bbt() wrapper * Protect access to rawnand devices while in suspend * bindings: Document the wp-gpios property Rax NAND controller driver changes: * atmel: Fix refcount issue in atmel_nand_controller_init * nandsim: - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern - Merge repeat codes in ns_switch_state - Replace overflow check with kzalloc to single kcalloc * rockchip: Fix platform_get_irq.cocci warning * stm32_fmc2: Add NAND Write Protect support * pl353: Set the nand chip node as the flash node * brcmnand: Fix sparse warnings in bcma_nand * omap_elm: Remove redundant variable 'errors' * gpmi: - Support fast edo timings for mx28 - Validate controller clock rate - Fix controller timings setting * brcmnand: - Add BCMA shim - BCMA controller uses command shift of 0 - Allow platform data instantation - Add platform data structure for BCMA - Allow working without interrupts - Move OF operations out of brcmnand_init_cs() - Avoid pdev in brcmnand_init_cs() - Allow SoC to provide I/O operations - Assign soc as early as possible Onenand changes: * Check for error irq SPI-NAND core changes: * Delay a little bit the dirmap creation * Create direct mapping descriptors for ECC operations SPI-NAND driver changes: * macronix: Use random program load SPI NOR core changes: * Move vendor specific code out of the core into vendor drivers. * Unify all function and object names in the vendor modules. * Make setup() callback optional to improve readability. * Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash declaration. SPI changes: * Macronix SPI controller: - Fix the transmit path - Create a helper to configure the controller before an operation - Create a helper to ease the start of an operation - Add support for direct mapping - Add support for pipelined ECC operations * spi-mem: - Introduce a capability structure - Check the controller extra capabilities - cadence-quadspi/mxic: Provide capability structures - Kill the spi_mem_dtr_supports_op() helper - Add an ecc parameter to the spi_mem_op structure Binding changes: * Dropped mtd/cortina,gemini-flash.txt * Convert BCM47xx partitions to json-schema * Vendor prefixes: Clarify Macronix prefix * SPI NAND: Convert spi-nand description file to yaml * Raw NAND chip: Create a NAND chip description * Raw NAND controller: - Harmonize the property types - Fix a comment in the examples - Fix the reg property description * Describe Macronix NAND ECC engine * Macronix SPI controller: - Document the nand-ecc-engine property - Convert to yaml - The interrupt property is not mandatory -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAmI7WJcACgkQJWrqGEe9 VoSzpAgAutzRv9TRUiXdBGGlJ851QaZ6ZUvT1bHKTQA+xZi+MZyNmc0cWNg3B70I PnwyxNAmRkUQKwV5Vgy/sQrt42qZnPmr+8XMq+UiziPmgFdjiTdLqGcN619Hi12t JqtoKL828R064LSEq5nWsJ2waoGT1nNtZK8kA2qe8ctvmH0YTThriVZUQR4/Befb OGFheceLFycE/vkktPPr3As4603fMiyDOT7EA3Mtzgjohry0a0TqoakHCaHC/fYo 0/h+x+jJATPtgbWm1ZiV3cZ/Su00+rKuQOsiAWvM/pqDaijsVntBmtK0PRtums2Q m8LCspuQYNnCINeQXqba9RxACpibDg== =+6Zk -----END PGP SIGNATURE----- Merge tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "There has been a lot of activity in the MTD subsystem recently, with a number of SPI-NOR cleanups as well as the introduction of ECC engines that can be used by SPI controllers (hence a few SPI patches in here). Core MTD changes: - Replace the expert mode symbols with a single helper - Fix misuses of of_match_ptr() - Remove partid and partname debugfs files - tests: Fix eraseblock read speed miscalculation for lower partition sizes - TRX parser: Allow to use on MediaTek MIPS SoCs MTD driver changes: - spear_smi: use GFP_KERNEL - mchp48l640: Add SPI ID table - mchp23k256: Add SPI ID table - blkdevs: Avoid soft lockups with some mtd/spi devices - aspeed-smc: Improve probe resilience Hyperbus changes: - HBMC_AM654 should depend on ARCH_K3 NAND core changes: - ECC: - Add infrastructure to support hardware engines - Add a new helper to retrieve the ECC context - Provide a helper to retrieve a pilelined engine device NAND-ECC changes: - Macronix ECC engine: - Add Macronix external ECC engine support - Support SPI pipelined mode - Make two read-only arrays static const - Fix compile test issue Raw NAND core changes: - Fix misuses of of_match_node() - Rework of_get_nand_bus_width() - Remove of_get_nand_on_flash_bbt() wrapper - Protect access to rawnand devices while in suspend - bindings: Document the wp-gpios property Rax NAND controller driver changes: - atmel: Fix refcount issue in atmel_nand_controller_init - nandsim: - Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern - Merge repeat codes in ns_switch_state - Replace overflow check with kzalloc to single kcalloc - rockchip: Fix platform_get_irq.cocci warning - stm32_fmc2: Add NAND Write Protect support - pl353: Set the nand chip node as the flash node - brcmnand: Fix sparse warnings in bcma_nand - omap_elm: Remove redundant variable 'errors' - gpmi: - Support fast edo timings for mx28 - Validate controller clock rate - Fix controller timings setting - brcmnand: - Add BCMA shim - BCMA controller uses command shift of 0 - Allow platform data instantation - Add platform data structure for BCMA - Allow working without interrupts - Move OF operations out of brcmnand_init_cs() - Avoid pdev in brcmnand_init_cs() - Allow SoC to provide I/O operations - Assign soc as early as possible Onenand changes: - Check for error irq SPI-NAND core changes: - Delay a little bit the dirmap creation - Create direct mapping descriptors for ECC operations SPI-NAND driver changes: - macronix: Use random program load SPI NOR core changes: - Move vendor specific code out of the core into vendor drivers. - Unify all function and object names in the vendor modules. - Make setup() callback optional to improve readability. - Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash declaration. SPI changes: - Macronix SPI controller: - Fix the transmit path - Create a helper to configure the controller before an operation - Create a helper to ease the start of an operation - Add support for direct mapping - Add support for pipelined ECC operations - spi-mem: - Introduce a capability structure - Check the controller extra capabilities - cadence-quadspi/mxic: Provide capability structures - Kill the spi_mem_dtr_supports_op() helper - Add an ecc parameter to the spi_mem_op structure Binding changes: - Dropped mtd/cortina,gemini-flash.txt - Convert BCM47xx partitions to json-schema - Vendor prefixes: Clarify Macronix prefix - SPI NAND: Convert spi-nand description file to yaml - Raw NAND chip: Create a NAND chip description - Raw NAND controller: - Harmonize the property types - Fix a comment in the examples - Fix the reg property description - Describe Macronix NAND ECC engine - Macronix SPI controller: - Document the nand-ecc-engine property - Convert to yaml - The interrupt property is not mandatory" * tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits) mtd: nand: ecc: mxic: Fix compile test issue mtd: nand: mxic-ecc: make two read-only arrays static const mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3 mtd: core: Remove partid and partname debugfs files dt-bindings: mtd: partitions: convert BCM47xx to the json-schema mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init mtd: rawnand: rockchip: fix platform_get_irq.cocci warning mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set mtd: spi-nor: renumber flags mtd: spi-nor: slightly change code style in spi_nor_sr_ready() mtd: spi-nor: spansion: rename vendor specific functions and defines mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag mtd: spi-nor: move all spansion specifics into spansion.c mtd: spi-nor: spansion: slightly rework control flow in late_init() mtd: spi-nor: micron-st: rename vendor specific functions and defines mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag mtd: spi-nor: move all micron-st specifics into micron-st.c mtd: spi-nor: xilinx: correct the debug message mtd: spi-nor: xilinx: rename vendor specific functions and defines ...
911 lines
24 KiB
C
911 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Exceet Electronics GmbH
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* Copyright (C) 2018 Bootlin
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*
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* Author: Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#include <linux/dmaengine.h>
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#include <linux/iopoll.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#include "internals.h"
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#define SPI_MEM_MAX_BUSWIDTH 8
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/**
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* spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
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* memory operation
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* @ctlr: the SPI controller requesting this dma_map()
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* @op: the memory operation containing the buffer to map
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* @sgt: a pointer to a non-initialized sg_table that will be filled by this
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* function
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*
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* Some controllers might want to do DMA on the data buffer embedded in @op.
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* This helper prepares everything for you and provides a ready-to-use
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* sg_table. This function is not intended to be called from spi drivers.
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* Only SPI controller drivers should use it.
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* Note that the caller must ensure the memory region pointed by
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* op->data.buf.{in,out} is DMA-able before calling this function.
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*
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* Return: 0 in case of success, a negative error code otherwise.
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*/
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int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
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const struct spi_mem_op *op,
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struct sg_table *sgt)
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{
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struct device *dmadev;
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if (!op->data.nbytes)
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return -EINVAL;
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if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
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dmadev = ctlr->dma_tx->device->dev;
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else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
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dmadev = ctlr->dma_rx->device->dev;
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else
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dmadev = ctlr->dev.parent;
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if (!dmadev)
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return -EINVAL;
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return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes,
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op->data.dir == SPI_MEM_DATA_IN ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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}
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EXPORT_SYMBOL_GPL(spi_controller_dma_map_mem_op_data);
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/**
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* spi_controller_dma_unmap_mem_op_data() - DMA-unmap the buffer attached to a
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* memory operation
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* @ctlr: the SPI controller requesting this dma_unmap()
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* @op: the memory operation containing the buffer to unmap
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* @sgt: a pointer to an sg_table previously initialized by
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* spi_controller_dma_map_mem_op_data()
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*
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* Some controllers might want to do DMA on the data buffer embedded in @op.
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* This helper prepares things so that the CPU can access the
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* op->data.buf.{in,out} buffer again.
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*
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* This function is not intended to be called from SPI drivers. Only SPI
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* controller drivers should use it.
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*
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* This function should be called after the DMA operation has finished and is
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* only valid if the previous spi_controller_dma_map_mem_op_data() call
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* returned 0.
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*
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* Return: 0 in case of success, a negative error code otherwise.
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*/
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void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
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const struct spi_mem_op *op,
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struct sg_table *sgt)
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{
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struct device *dmadev;
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if (!op->data.nbytes)
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return;
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if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
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dmadev = ctlr->dma_tx->device->dev;
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else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
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dmadev = ctlr->dma_rx->device->dev;
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else
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dmadev = ctlr->dev.parent;
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spi_unmap_buf(ctlr, dmadev, sgt,
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op->data.dir == SPI_MEM_DATA_IN ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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}
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EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data);
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static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx)
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{
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u32 mode = mem->spi->mode;
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switch (buswidth) {
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case 1:
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return 0;
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case 2:
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if ((tx &&
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(mode & (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL))) ||
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(!tx &&
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(mode & (SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL))))
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return 0;
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break;
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case 4:
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if ((tx && (mode & (SPI_TX_QUAD | SPI_TX_OCTAL))) ||
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(!tx && (mode & (SPI_RX_QUAD | SPI_RX_OCTAL))))
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return 0;
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break;
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case 8:
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if ((tx && (mode & SPI_TX_OCTAL)) ||
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(!tx && (mode & SPI_RX_OCTAL)))
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return 0;
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break;
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default:
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break;
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}
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return -ENOTSUPP;
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}
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static bool spi_mem_check_buswidth(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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if (spi_check_buswidth_req(mem, op->cmd.buswidth, true))
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return false;
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if (op->addr.nbytes &&
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spi_check_buswidth_req(mem, op->addr.buswidth, true))
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return false;
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if (op->dummy.nbytes &&
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spi_check_buswidth_req(mem, op->dummy.buswidth, true))
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return false;
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if (op->data.dir != SPI_MEM_NO_DATA &&
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spi_check_buswidth_req(mem, op->data.buswidth,
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op->data.dir == SPI_MEM_DATA_OUT))
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return false;
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return true;
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}
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bool spi_mem_default_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct spi_controller *ctlr = mem->spi->controller;
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bool op_is_dtr =
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op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
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if (op_is_dtr) {
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if (!spi_mem_controller_is_capable(ctlr, dtr))
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return false;
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if (op->cmd.nbytes != 2)
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return false;
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} else {
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if (op->cmd.nbytes != 1)
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return false;
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}
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if (op->data.ecc) {
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if (!spi_mem_controller_is_capable(ctlr, ecc))
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return false;
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}
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return spi_mem_check_buswidth(mem, op);
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}
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EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
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static bool spi_mem_buswidth_is_valid(u8 buswidth)
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{
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if (hweight8(buswidth) > 1 || buswidth > SPI_MEM_MAX_BUSWIDTH)
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return false;
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return true;
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}
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static int spi_mem_check_op(const struct spi_mem_op *op)
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{
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if (!op->cmd.buswidth || !op->cmd.nbytes)
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return -EINVAL;
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if ((op->addr.nbytes && !op->addr.buswidth) ||
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(op->dummy.nbytes && !op->dummy.buswidth) ||
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(op->data.nbytes && !op->data.buswidth))
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return -EINVAL;
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if (!spi_mem_buswidth_is_valid(op->cmd.buswidth) ||
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!spi_mem_buswidth_is_valid(op->addr.buswidth) ||
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!spi_mem_buswidth_is_valid(op->dummy.buswidth) ||
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!spi_mem_buswidth_is_valid(op->data.buswidth))
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return -EINVAL;
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return 0;
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}
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static bool spi_mem_internal_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct spi_controller *ctlr = mem->spi->controller;
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if (ctlr->mem_ops && ctlr->mem_ops->supports_op)
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return ctlr->mem_ops->supports_op(mem, op);
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return spi_mem_default_supports_op(mem, op);
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}
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/**
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* spi_mem_supports_op() - Check if a memory device and the controller it is
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* connected to support a specific memory operation
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* @mem: the SPI memory
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* @op: the memory operation to check
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*
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* Some controllers are only supporting Single or Dual IOs, others might only
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* support specific opcodes, or it can even be that the controller and device
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* both support Quad IOs but the hardware prevents you from using it because
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* only 2 IO lines are connected.
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*
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* This function checks whether a specific operation is supported.
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*
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* Return: true if @op is supported, false otherwise.
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*/
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bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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if (spi_mem_check_op(op))
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return false;
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return spi_mem_internal_supports_op(mem, op);
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}
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EXPORT_SYMBOL_GPL(spi_mem_supports_op);
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static int spi_mem_access_start(struct spi_mem *mem)
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{
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struct spi_controller *ctlr = mem->spi->controller;
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/*
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* Flush the message queue before executing our SPI memory
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* operation to prevent preemption of regular SPI transfers.
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*/
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spi_flush_queue(ctlr);
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if (ctlr->auto_runtime_pm) {
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int ret;
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ret = pm_runtime_get_sync(ctlr->dev.parent);
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if (ret < 0) {
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pm_runtime_put_noidle(ctlr->dev.parent);
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dev_err(&ctlr->dev, "Failed to power device: %d\n",
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ret);
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return ret;
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}
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}
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mutex_lock(&ctlr->bus_lock_mutex);
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mutex_lock(&ctlr->io_mutex);
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return 0;
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}
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static void spi_mem_access_end(struct spi_mem *mem)
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{
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struct spi_controller *ctlr = mem->spi->controller;
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mutex_unlock(&ctlr->io_mutex);
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mutex_unlock(&ctlr->bus_lock_mutex);
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if (ctlr->auto_runtime_pm)
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pm_runtime_put(ctlr->dev.parent);
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}
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/**
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* spi_mem_exec_op() - Execute a memory operation
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* @mem: the SPI memory
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* @op: the memory operation to execute
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*
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* Executes a memory operation.
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*
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* This function first checks that @op is supported and then tries to execute
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* it.
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*
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* Return: 0 in case of success, a negative error code otherwise.
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*/
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int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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unsigned int tmpbufsize, xferpos = 0, totalxferlen = 0;
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struct spi_controller *ctlr = mem->spi->controller;
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struct spi_transfer xfers[4] = { };
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struct spi_message msg;
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u8 *tmpbuf;
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int ret;
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ret = spi_mem_check_op(op);
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if (ret)
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return ret;
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if (!spi_mem_internal_supports_op(mem, op))
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return -ENOTSUPP;
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if (ctlr->mem_ops && !mem->spi->cs_gpiod) {
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ret = spi_mem_access_start(mem);
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if (ret)
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return ret;
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ret = ctlr->mem_ops->exec_op(mem, op);
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spi_mem_access_end(mem);
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/*
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* Some controllers only optimize specific paths (typically the
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* read path) and expect the core to use the regular SPI
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* interface in other cases.
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*/
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if (!ret || ret != -ENOTSUPP)
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return ret;
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}
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tmpbufsize = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
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/*
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* Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so
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* we're guaranteed that this buffer is DMA-able, as required by the
|
|
* SPI layer.
|
|
*/
|
|
tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA);
|
|
if (!tmpbuf)
|
|
return -ENOMEM;
|
|
|
|
spi_message_init(&msg);
|
|
|
|
tmpbuf[0] = op->cmd.opcode;
|
|
xfers[xferpos].tx_buf = tmpbuf;
|
|
xfers[xferpos].len = op->cmd.nbytes;
|
|
xfers[xferpos].tx_nbits = op->cmd.buswidth;
|
|
spi_message_add_tail(&xfers[xferpos], &msg);
|
|
xferpos++;
|
|
totalxferlen++;
|
|
|
|
if (op->addr.nbytes) {
|
|
int i;
|
|
|
|
for (i = 0; i < op->addr.nbytes; i++)
|
|
tmpbuf[i + 1] = op->addr.val >>
|
|
(8 * (op->addr.nbytes - i - 1));
|
|
|
|
xfers[xferpos].tx_buf = tmpbuf + 1;
|
|
xfers[xferpos].len = op->addr.nbytes;
|
|
xfers[xferpos].tx_nbits = op->addr.buswidth;
|
|
spi_message_add_tail(&xfers[xferpos], &msg);
|
|
xferpos++;
|
|
totalxferlen += op->addr.nbytes;
|
|
}
|
|
|
|
if (op->dummy.nbytes) {
|
|
memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes);
|
|
xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
|
|
xfers[xferpos].len = op->dummy.nbytes;
|
|
xfers[xferpos].tx_nbits = op->dummy.buswidth;
|
|
xfers[xferpos].dummy_data = 1;
|
|
spi_message_add_tail(&xfers[xferpos], &msg);
|
|
xferpos++;
|
|
totalxferlen += op->dummy.nbytes;
|
|
}
|
|
|
|
if (op->data.nbytes) {
|
|
if (op->data.dir == SPI_MEM_DATA_IN) {
|
|
xfers[xferpos].rx_buf = op->data.buf.in;
|
|
xfers[xferpos].rx_nbits = op->data.buswidth;
|
|
} else {
|
|
xfers[xferpos].tx_buf = op->data.buf.out;
|
|
xfers[xferpos].tx_nbits = op->data.buswidth;
|
|
}
|
|
|
|
xfers[xferpos].len = op->data.nbytes;
|
|
spi_message_add_tail(&xfers[xferpos], &msg);
|
|
xferpos++;
|
|
totalxferlen += op->data.nbytes;
|
|
}
|
|
|
|
ret = spi_sync(mem->spi, &msg);
|
|
|
|
kfree(tmpbuf);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (msg.actual_length != totalxferlen)
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_exec_op);
|
|
|
|
/**
|
|
* spi_mem_get_name() - Return the SPI mem device name to be used by the
|
|
* upper layer if necessary
|
|
* @mem: the SPI memory
|
|
*
|
|
* This function allows SPI mem users to retrieve the SPI mem device name.
|
|
* It is useful if the upper layer needs to expose a custom name for
|
|
* compatibility reasons.
|
|
*
|
|
* Return: a string containing the name of the memory device to be used
|
|
* by the SPI mem user
|
|
*/
|
|
const char *spi_mem_get_name(struct spi_mem *mem)
|
|
{
|
|
return mem->name;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_get_name);
|
|
|
|
/**
|
|
* spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
|
|
* match controller limitations
|
|
* @mem: the SPI memory
|
|
* @op: the operation to adjust
|
|
*
|
|
* Some controllers have FIFO limitations and must split a data transfer
|
|
* operation into multiple ones, others require a specific alignment for
|
|
* optimized accesses. This function allows SPI mem drivers to split a single
|
|
* operation into multiple sub-operations when required.
|
|
*
|
|
* Return: a negative error code if the controller can't properly adjust @op,
|
|
* 0 otherwise. Note that @op->data.nbytes will be updated if @op
|
|
* can't be handled in a single step.
|
|
*/
|
|
int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
|
|
{
|
|
struct spi_controller *ctlr = mem->spi->controller;
|
|
size_t len;
|
|
|
|
if (ctlr->mem_ops && ctlr->mem_ops->adjust_op_size)
|
|
return ctlr->mem_ops->adjust_op_size(mem, op);
|
|
|
|
if (!ctlr->mem_ops || !ctlr->mem_ops->exec_op) {
|
|
len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
|
|
|
|
if (len > spi_max_transfer_size(mem->spi))
|
|
return -EINVAL;
|
|
|
|
op->data.nbytes = min3((size_t)op->data.nbytes,
|
|
spi_max_transfer_size(mem->spi),
|
|
spi_max_message_size(mem->spi) -
|
|
len);
|
|
if (!op->data.nbytes)
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
|
|
|
|
static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
|
|
u64 offs, size_t len, void *buf)
|
|
{
|
|
struct spi_mem_op op = desc->info.op_tmpl;
|
|
int ret;
|
|
|
|
op.addr.val = desc->info.offset + offs;
|
|
op.data.buf.in = buf;
|
|
op.data.nbytes = len;
|
|
ret = spi_mem_adjust_op_size(desc->mem, &op);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = spi_mem_exec_op(desc->mem, &op);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return op.data.nbytes;
|
|
}
|
|
|
|
static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc,
|
|
u64 offs, size_t len, const void *buf)
|
|
{
|
|
struct spi_mem_op op = desc->info.op_tmpl;
|
|
int ret;
|
|
|
|
op.addr.val = desc->info.offset + offs;
|
|
op.data.buf.out = buf;
|
|
op.data.nbytes = len;
|
|
ret = spi_mem_adjust_op_size(desc->mem, &op);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = spi_mem_exec_op(desc->mem, &op);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return op.data.nbytes;
|
|
}
|
|
|
|
/**
|
|
* spi_mem_dirmap_create() - Create a direct mapping descriptor
|
|
* @mem: SPI mem device this direct mapping should be created for
|
|
* @info: direct mapping information
|
|
*
|
|
* This function is creating a direct mapping descriptor which can then be used
|
|
* to access the memory using spi_mem_dirmap_read() or spi_mem_dirmap_write().
|
|
* If the SPI controller driver does not support direct mapping, this function
|
|
* falls back to an implementation using spi_mem_exec_op(), so that the caller
|
|
* doesn't have to bother implementing a fallback on his own.
|
|
*
|
|
* Return: a valid pointer in case of success, and ERR_PTR() otherwise.
|
|
*/
|
|
struct spi_mem_dirmap_desc *
|
|
spi_mem_dirmap_create(struct spi_mem *mem,
|
|
const struct spi_mem_dirmap_info *info)
|
|
{
|
|
struct spi_controller *ctlr = mem->spi->controller;
|
|
struct spi_mem_dirmap_desc *desc;
|
|
int ret = -ENOTSUPP;
|
|
|
|
/* Make sure the number of address cycles is between 1 and 8 bytes. */
|
|
if (!info->op_tmpl.addr.nbytes || info->op_tmpl.addr.nbytes > 8)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
/* data.dir should either be SPI_MEM_DATA_IN or SPI_MEM_DATA_OUT. */
|
|
if (info->op_tmpl.data.dir == SPI_MEM_NO_DATA)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
|
|
if (!desc)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
desc->mem = mem;
|
|
desc->info = *info;
|
|
if (ctlr->mem_ops && ctlr->mem_ops->dirmap_create)
|
|
ret = ctlr->mem_ops->dirmap_create(desc);
|
|
|
|
if (ret) {
|
|
desc->nodirmap = true;
|
|
if (!spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
|
|
ret = -ENOTSUPP;
|
|
else
|
|
ret = 0;
|
|
}
|
|
|
|
if (ret) {
|
|
kfree(desc);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
return desc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_dirmap_create);
|
|
|
|
/**
|
|
* spi_mem_dirmap_destroy() - Destroy a direct mapping descriptor
|
|
* @desc: the direct mapping descriptor to destroy
|
|
*
|
|
* This function destroys a direct mapping descriptor previously created by
|
|
* spi_mem_dirmap_create().
|
|
*/
|
|
void spi_mem_dirmap_destroy(struct spi_mem_dirmap_desc *desc)
|
|
{
|
|
struct spi_controller *ctlr = desc->mem->spi->controller;
|
|
|
|
if (!desc->nodirmap && ctlr->mem_ops && ctlr->mem_ops->dirmap_destroy)
|
|
ctlr->mem_ops->dirmap_destroy(desc);
|
|
|
|
kfree(desc);
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_dirmap_destroy);
|
|
|
|
static void devm_spi_mem_dirmap_release(struct device *dev, void *res)
|
|
{
|
|
struct spi_mem_dirmap_desc *desc = *(struct spi_mem_dirmap_desc **)res;
|
|
|
|
spi_mem_dirmap_destroy(desc);
|
|
}
|
|
|
|
/**
|
|
* devm_spi_mem_dirmap_create() - Create a direct mapping descriptor and attach
|
|
* it to a device
|
|
* @dev: device the dirmap desc will be attached to
|
|
* @mem: SPI mem device this direct mapping should be created for
|
|
* @info: direct mapping information
|
|
*
|
|
* devm_ variant of the spi_mem_dirmap_create() function. See
|
|
* spi_mem_dirmap_create() for more details.
|
|
*
|
|
* Return: a valid pointer in case of success, and ERR_PTR() otherwise.
|
|
*/
|
|
struct spi_mem_dirmap_desc *
|
|
devm_spi_mem_dirmap_create(struct device *dev, struct spi_mem *mem,
|
|
const struct spi_mem_dirmap_info *info)
|
|
{
|
|
struct spi_mem_dirmap_desc **ptr, *desc;
|
|
|
|
ptr = devres_alloc(devm_spi_mem_dirmap_release, sizeof(*ptr),
|
|
GFP_KERNEL);
|
|
if (!ptr)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
desc = spi_mem_dirmap_create(mem, info);
|
|
if (IS_ERR(desc)) {
|
|
devres_free(ptr);
|
|
} else {
|
|
*ptr = desc;
|
|
devres_add(dev, ptr);
|
|
}
|
|
|
|
return desc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(devm_spi_mem_dirmap_create);
|
|
|
|
static int devm_spi_mem_dirmap_match(struct device *dev, void *res, void *data)
|
|
{
|
|
struct spi_mem_dirmap_desc **ptr = res;
|
|
|
|
if (WARN_ON(!ptr || !*ptr))
|
|
return 0;
|
|
|
|
return *ptr == data;
|
|
}
|
|
|
|
/**
|
|
* devm_spi_mem_dirmap_destroy() - Destroy a direct mapping descriptor attached
|
|
* to a device
|
|
* @dev: device the dirmap desc is attached to
|
|
* @desc: the direct mapping descriptor to destroy
|
|
*
|
|
* devm_ variant of the spi_mem_dirmap_destroy() function. See
|
|
* spi_mem_dirmap_destroy() for more details.
|
|
*/
|
|
void devm_spi_mem_dirmap_destroy(struct device *dev,
|
|
struct spi_mem_dirmap_desc *desc)
|
|
{
|
|
devres_release(dev, devm_spi_mem_dirmap_release,
|
|
devm_spi_mem_dirmap_match, desc);
|
|
}
|
|
EXPORT_SYMBOL_GPL(devm_spi_mem_dirmap_destroy);
|
|
|
|
/**
|
|
* spi_mem_dirmap_read() - Read data through a direct mapping
|
|
* @desc: direct mapping descriptor
|
|
* @offs: offset to start reading from. Note that this is not an absolute
|
|
* offset, but the offset within the direct mapping which already has
|
|
* its own offset
|
|
* @len: length in bytes
|
|
* @buf: destination buffer. This buffer must be DMA-able
|
|
*
|
|
* This function reads data from a memory device using a direct mapping
|
|
* previously instantiated with spi_mem_dirmap_create().
|
|
*
|
|
* Return: the amount of data read from the memory device or a negative error
|
|
* code. Note that the returned size might be smaller than @len, and the caller
|
|
* is responsible for calling spi_mem_dirmap_read() again when that happens.
|
|
*/
|
|
ssize_t spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
|
|
u64 offs, size_t len, void *buf)
|
|
{
|
|
struct spi_controller *ctlr = desc->mem->spi->controller;
|
|
ssize_t ret;
|
|
|
|
if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
|
|
return -EINVAL;
|
|
|
|
if (!len)
|
|
return 0;
|
|
|
|
if (desc->nodirmap) {
|
|
ret = spi_mem_no_dirmap_read(desc, offs, len, buf);
|
|
} else if (ctlr->mem_ops && ctlr->mem_ops->dirmap_read) {
|
|
ret = spi_mem_access_start(desc->mem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ctlr->mem_ops->dirmap_read(desc, offs, len, buf);
|
|
|
|
spi_mem_access_end(desc->mem);
|
|
} else {
|
|
ret = -ENOTSUPP;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_dirmap_read);
|
|
|
|
/**
|
|
* spi_mem_dirmap_write() - Write data through a direct mapping
|
|
* @desc: direct mapping descriptor
|
|
* @offs: offset to start writing from. Note that this is not an absolute
|
|
* offset, but the offset within the direct mapping which already has
|
|
* its own offset
|
|
* @len: length in bytes
|
|
* @buf: source buffer. This buffer must be DMA-able
|
|
*
|
|
* This function writes data to a memory device using a direct mapping
|
|
* previously instantiated with spi_mem_dirmap_create().
|
|
*
|
|
* Return: the amount of data written to the memory device or a negative error
|
|
* code. Note that the returned size might be smaller than @len, and the caller
|
|
* is responsible for calling spi_mem_dirmap_write() again when that happens.
|
|
*/
|
|
ssize_t spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
|
|
u64 offs, size_t len, const void *buf)
|
|
{
|
|
struct spi_controller *ctlr = desc->mem->spi->controller;
|
|
ssize_t ret;
|
|
|
|
if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_OUT)
|
|
return -EINVAL;
|
|
|
|
if (!len)
|
|
return 0;
|
|
|
|
if (desc->nodirmap) {
|
|
ret = spi_mem_no_dirmap_write(desc, offs, len, buf);
|
|
} else if (ctlr->mem_ops && ctlr->mem_ops->dirmap_write) {
|
|
ret = spi_mem_access_start(desc->mem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ctlr->mem_ops->dirmap_write(desc, offs, len, buf);
|
|
|
|
spi_mem_access_end(desc->mem);
|
|
} else {
|
|
ret = -ENOTSUPP;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_dirmap_write);
|
|
|
|
static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv)
|
|
{
|
|
return container_of(drv, struct spi_mem_driver, spidrv.driver);
|
|
}
|
|
|
|
static int spi_mem_read_status(struct spi_mem *mem,
|
|
const struct spi_mem_op *op,
|
|
u16 *status)
|
|
{
|
|
const u8 *bytes = (u8 *)op->data.buf.in;
|
|
int ret;
|
|
|
|
ret = spi_mem_exec_op(mem, op);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (op->data.nbytes > 1)
|
|
*status = ((u16)bytes[0] << 8) | bytes[1];
|
|
else
|
|
*status = bytes[0];
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* spi_mem_poll_status() - Poll memory device status
|
|
* @mem: SPI memory device
|
|
* @op: the memory operation to execute
|
|
* @mask: status bitmask to ckeck
|
|
* @match: (status & mask) expected value
|
|
* @initial_delay_us: delay in us before starting to poll
|
|
* @polling_delay_us: time to sleep between reads in us
|
|
* @timeout_ms: timeout in milliseconds
|
|
*
|
|
* This function polls a status register and returns when
|
|
* (status & mask) == match or when the timeout has expired.
|
|
*
|
|
* Return: 0 in case of success, -ETIMEDOUT in case of error,
|
|
* -EOPNOTSUPP if not supported.
|
|
*/
|
|
int spi_mem_poll_status(struct spi_mem *mem,
|
|
const struct spi_mem_op *op,
|
|
u16 mask, u16 match,
|
|
unsigned long initial_delay_us,
|
|
unsigned long polling_delay_us,
|
|
u16 timeout_ms)
|
|
{
|
|
struct spi_controller *ctlr = mem->spi->controller;
|
|
int ret = -EOPNOTSUPP;
|
|
int read_status_ret;
|
|
u16 status;
|
|
|
|
if (op->data.nbytes < 1 || op->data.nbytes > 2 ||
|
|
op->data.dir != SPI_MEM_DATA_IN)
|
|
return -EINVAL;
|
|
|
|
if (ctlr->mem_ops && ctlr->mem_ops->poll_status) {
|
|
ret = spi_mem_access_start(mem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ctlr->mem_ops->poll_status(mem, op, mask, match,
|
|
initial_delay_us, polling_delay_us,
|
|
timeout_ms);
|
|
|
|
spi_mem_access_end(mem);
|
|
}
|
|
|
|
if (ret == -EOPNOTSUPP) {
|
|
if (!spi_mem_supports_op(mem, op))
|
|
return ret;
|
|
|
|
if (initial_delay_us < 10)
|
|
udelay(initial_delay_us);
|
|
else
|
|
usleep_range((initial_delay_us >> 2) + 1,
|
|
initial_delay_us);
|
|
|
|
ret = read_poll_timeout(spi_mem_read_status, read_status_ret,
|
|
(read_status_ret || ((status) & mask) == match),
|
|
polling_delay_us, timeout_ms * 1000, false, mem,
|
|
op, &status);
|
|
if (read_status_ret)
|
|
return read_status_ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_poll_status);
|
|
|
|
static int spi_mem_probe(struct spi_device *spi)
|
|
{
|
|
struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
|
struct spi_controller *ctlr = spi->controller;
|
|
struct spi_mem *mem;
|
|
|
|
mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL);
|
|
if (!mem)
|
|
return -ENOMEM;
|
|
|
|
mem->spi = spi;
|
|
|
|
if (ctlr->mem_ops && ctlr->mem_ops->get_name)
|
|
mem->name = ctlr->mem_ops->get_name(mem);
|
|
else
|
|
mem->name = dev_name(&spi->dev);
|
|
|
|
if (IS_ERR_OR_NULL(mem->name))
|
|
return PTR_ERR_OR_ZERO(mem->name);
|
|
|
|
spi_set_drvdata(spi, mem);
|
|
|
|
return memdrv->probe(mem);
|
|
}
|
|
|
|
static void spi_mem_remove(struct spi_device *spi)
|
|
{
|
|
struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
|
struct spi_mem *mem = spi_get_drvdata(spi);
|
|
|
|
if (memdrv->remove)
|
|
memdrv->remove(mem);
|
|
}
|
|
|
|
static void spi_mem_shutdown(struct spi_device *spi)
|
|
{
|
|
struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
|
struct spi_mem *mem = spi_get_drvdata(spi);
|
|
|
|
if (memdrv->shutdown)
|
|
memdrv->shutdown(mem);
|
|
}
|
|
|
|
/**
|
|
* spi_mem_driver_register_with_owner() - Register a SPI memory driver
|
|
* @memdrv: the SPI memory driver to register
|
|
* @owner: the owner of this driver
|
|
*
|
|
* Registers a SPI memory driver.
|
|
*
|
|
* Return: 0 in case of success, a negative error core otherwise.
|
|
*/
|
|
|
|
int spi_mem_driver_register_with_owner(struct spi_mem_driver *memdrv,
|
|
struct module *owner)
|
|
{
|
|
memdrv->spidrv.probe = spi_mem_probe;
|
|
memdrv->spidrv.remove = spi_mem_remove;
|
|
memdrv->spidrv.shutdown = spi_mem_shutdown;
|
|
|
|
return __spi_register_driver(owner, &memdrv->spidrv);
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_driver_register_with_owner);
|
|
|
|
/**
|
|
* spi_mem_driver_unregister() - Unregister a SPI memory driver
|
|
* @memdrv: the SPI memory driver to unregister
|
|
*
|
|
* Unregisters a SPI memory driver.
|
|
*/
|
|
void spi_mem_driver_unregister(struct spi_mem_driver *memdrv)
|
|
{
|
|
spi_unregister_driver(&memdrv->spidrv);
|
|
}
|
|
EXPORT_SYMBOL_GPL(spi_mem_driver_unregister);
|