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725b0e3ea8
Mostly due to a long driver history it's methods and macro names look a
bit messy. In particularly that concerns the code their prefixes. A
biggest part of the driver functions and macros have got the dw_spi/DW_SPI
prefixes. But there are some entities which have been just
"spi_/SPI_"-prefixed. Especially that concerns the CSR and their fields
macro definitions. It makes the code harder to comprehend since such
methods and macros can be easily confused with the global SPI-subsystem
exports. In this case the only possible way to more or less quickly
distinguish one naming space from another is either by context or by the
argument type, which most of the times isn't that easy anyway. In addition
to that a new DW SSI IP-core support has been added in the framework of
commit e539f435cb
("spi: dw: Add support for DesignWare DWC_ssi"), which
introduced a new set or macro-prefixes to describe CTRLR0-specific fields
and worsen the situation. Finally there are methods with
no DW SPI driver-reference prefix at all, that make the code reading even
harder. So in order to ease the driver hacking let's bring the code naming
to a common base:
1) Each method is supposed to have "dw_spi_" prefix so to be easily
distinguished from the kernel API, e.g. SPI-subsystem methods and macros.
(Exception is the local implementation of the readl/writel methods since
being just the regspace accessors.)
2) Each generically used macro should have DW_SPI_-prefix thus being
easily comprehended as the local driver definition.
3) DW APB SSI and DW SSI specific macros should have prefixes as DW_PSSI_
and DW_HSSI_ respectively so referring to the system buses they support
(APB and AHB similarly to the DT clocks naming like pclk, hclk).
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20211115181917.7521-4-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
343 lines
8.6 KiB
C
343 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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//
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// Authors:
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// Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
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// Serge Semin <Sergey.Semin@baikalelectronics.ru>
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//
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// Baikal-T1 DW APB SPI and System Boot SPI driver
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//
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#include <linux/clk.h>
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#include <linux/cpumask.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mux/consumer.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include <linux/slab.h>
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#include <linux/spi/spi-mem.h>
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#include <linux/spi/spi.h>
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#include "spi-dw.h"
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#define BT1_BOOT_DIRMAP 0
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#define BT1_BOOT_REGS 1
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struct dw_spi_bt1 {
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struct dw_spi dws;
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struct clk *clk;
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struct mux_control *mux;
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#ifdef CONFIG_SPI_DW_BT1_DIRMAP
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void __iomem *map;
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resource_size_t map_len;
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#endif
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};
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#define to_dw_spi_bt1(_ctlr) \
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container_of(spi_controller_get_devdata(_ctlr), struct dw_spi_bt1, dws)
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typedef int (*dw_spi_bt1_init_cb)(struct platform_device *pdev,
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struct dw_spi_bt1 *dwsbt1);
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#ifdef CONFIG_SPI_DW_BT1_DIRMAP
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static int dw_spi_bt1_dirmap_create(struct spi_mem_dirmap_desc *desc)
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{
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struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
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if (!dwsbt1->map ||
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!dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl))
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return -EOPNOTSUPP;
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/*
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* Make sure the requested region doesn't go out of the physically
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* mapped flash memory bounds and the operation is read-only.
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*/
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if (desc->info.offset + desc->info.length > dwsbt1->map_len ||
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desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
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return -EOPNOTSUPP;
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return 0;
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}
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/*
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* Directly mapped SPI memory region is only accessible in the dword chunks.
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* That's why we have to create a dedicated read-method to copy data from there
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* to the passed buffer.
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*/
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static void dw_spi_bt1_dirmap_copy_from_map(void *to, void __iomem *from, size_t len)
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{
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size_t shift, chunk;
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u32 data;
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/*
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* We split the copying up into the next three stages: unaligned head,
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* aligned body, unaligned tail.
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*/
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shift = (size_t)from & 0x3;
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if (shift) {
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chunk = min_t(size_t, 4 - shift, len);
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data = readl_relaxed(from - shift);
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memcpy(to, (char *)&data + shift, chunk);
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from += chunk;
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to += chunk;
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len -= chunk;
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}
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while (len >= 4) {
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data = readl_relaxed(from);
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memcpy(to, &data, 4);
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from += 4;
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to += 4;
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len -= 4;
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}
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if (len) {
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data = readl_relaxed(from);
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memcpy(to, &data, len);
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}
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}
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static ssize_t dw_spi_bt1_dirmap_read(struct spi_mem_dirmap_desc *desc,
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u64 offs, size_t len, void *buf)
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{
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struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
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struct dw_spi *dws = &dwsbt1->dws;
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struct spi_mem *mem = desc->mem;
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struct dw_spi_cfg cfg;
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int ret;
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/*
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* Make sure the requested operation length is valid. Truncate the
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* length if it's greater than the length of the MMIO region.
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*/
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if (offs >= dwsbt1->map_len || !len)
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return 0;
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len = min_t(size_t, len, dwsbt1->map_len - offs);
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/* Collect the controller configuration required by the operation */
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cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD;
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cfg.dfs = 8;
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cfg.ndf = 4;
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cfg.freq = mem->spi->max_speed_hz;
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/* Make sure the corresponding CS is de-asserted on transmission */
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dw_spi_set_cs(mem->spi, false);
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dw_spi_enable_chip(dws, 0);
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dw_spi_update_config(dws, mem->spi, &cfg);
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dw_spi_umask_intr(dws, DW_SPI_INT_RXFI);
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dw_spi_enable_chip(dws, 1);
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/*
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* Enable the transparent mode of the System Boot Controller.
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* The SPI core IO should have been locked before calling this method
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* so noone would be touching the controller' registers during the
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* dirmap operation.
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*/
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ret = mux_control_select(dwsbt1->mux, BT1_BOOT_DIRMAP);
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if (ret)
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return ret;
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dw_spi_bt1_dirmap_copy_from_map(buf, dwsbt1->map + offs, len);
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mux_control_deselect(dwsbt1->mux);
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dw_spi_set_cs(mem->spi, true);
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ret = dw_spi_check_status(dws, true);
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return ret ?: len;
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}
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#endif /* CONFIG_SPI_DW_BT1_DIRMAP */
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static int dw_spi_bt1_std_init(struct platform_device *pdev,
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struct dw_spi_bt1 *dwsbt1)
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{
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struct dw_spi *dws = &dwsbt1->dws;
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dws->irq = platform_get_irq(pdev, 0);
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if (dws->irq < 0)
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return dws->irq;
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dws->num_cs = 4;
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/*
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* Baikal-T1 Normal SPI Controllers don't always keep up with full SPI
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* bus speed especially when it comes to the concurrent access to the
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* APB bus resources. Thus we have no choice but to set a constraint on
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* the SPI bus frequency for the memory operations which require to
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* read/write data as fast as possible.
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*/
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dws->max_mem_freq = 20000000U;
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dw_spi_dma_setup_generic(dws);
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return 0;
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}
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static int dw_spi_bt1_sys_init(struct platform_device *pdev,
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struct dw_spi_bt1 *dwsbt1)
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{
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struct resource *mem __maybe_unused;
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struct dw_spi *dws = &dwsbt1->dws;
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/*
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* Baikal-T1 System Boot Controller is equipped with a mux, which
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* switches between the directly mapped SPI flash access mode and
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* IO access to the DW APB SSI registers. Note the mux controller
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* must be setup to preserve the registers being accessible by default
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* (on idle-state).
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*/
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dwsbt1->mux = devm_mux_control_get(&pdev->dev, NULL);
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if (IS_ERR(dwsbt1->mux))
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return PTR_ERR(dwsbt1->mux);
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/*
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* Directly mapped SPI flash memory is a 16MB MMIO region, which can be
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* used to access a peripheral memory device just by reading/writing
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* data from/to it. Note the system APB bus will stall during each IO
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* from/to the dirmap region until the operation is finished. So don't
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* use it concurrently with time-critical tasks (like the SPI memory
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* operations implemented in the DW APB SSI driver).
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*/
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#ifdef CONFIG_SPI_DW_BT1_DIRMAP
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (mem) {
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dwsbt1->map = devm_ioremap_resource(&pdev->dev, mem);
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if (!IS_ERR(dwsbt1->map)) {
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dwsbt1->map_len = resource_size(mem);
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dws->mem_ops.dirmap_create = dw_spi_bt1_dirmap_create;
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dws->mem_ops.dirmap_read = dw_spi_bt1_dirmap_read;
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} else {
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dwsbt1->map = NULL;
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}
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}
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#endif /* CONFIG_SPI_DW_BT1_DIRMAP */
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/*
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* There is no IRQ, no DMA and just one CS available on the System Boot
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* SPI controller.
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*/
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dws->irq = IRQ_NOTCONNECTED;
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dws->num_cs = 1;
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/*
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* Baikal-T1 System Boot SPI Controller doesn't keep up with the full
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* SPI bus speed due to relatively slow APB bus and races for it'
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* resources from different CPUs. The situation is worsen by a small
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* FIFOs depth (just 8 words). It works better in a single CPU mode
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* though, but still tends to be not fast enough at low CPU
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* frequencies.
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*/
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if (num_possible_cpus() > 1)
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dws->max_mem_freq = 10000000U;
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else
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dws->max_mem_freq = 20000000U;
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return 0;
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}
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static int dw_spi_bt1_probe(struct platform_device *pdev)
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{
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dw_spi_bt1_init_cb init_func;
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struct dw_spi_bt1 *dwsbt1;
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struct resource *mem;
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struct dw_spi *dws;
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int ret;
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dwsbt1 = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_bt1), GFP_KERNEL);
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if (!dwsbt1)
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return -ENOMEM;
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dws = &dwsbt1->dws;
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dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
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if (IS_ERR(dws->regs))
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return PTR_ERR(dws->regs);
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dws->paddr = mem->start;
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dwsbt1->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dwsbt1->clk))
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return PTR_ERR(dwsbt1->clk);
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ret = clk_prepare_enable(dwsbt1->clk);
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if (ret)
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return ret;
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dws->bus_num = pdev->id;
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dws->reg_io_width = 4;
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dws->max_freq = clk_get_rate(dwsbt1->clk);
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if (!dws->max_freq) {
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ret = -EINVAL;
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goto err_disable_clk;
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}
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init_func = device_get_match_data(&pdev->dev);
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ret = init_func(pdev, dwsbt1);
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if (ret)
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goto err_disable_clk;
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pm_runtime_enable(&pdev->dev);
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ret = dw_spi_add_host(&pdev->dev, dws);
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if (ret)
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goto err_disable_clk;
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platform_set_drvdata(pdev, dwsbt1);
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return 0;
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err_disable_clk:
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clk_disable_unprepare(dwsbt1->clk);
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return ret;
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}
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static int dw_spi_bt1_remove(struct platform_device *pdev)
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{
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struct dw_spi_bt1 *dwsbt1 = platform_get_drvdata(pdev);
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dw_spi_remove_host(&dwsbt1->dws);
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(dwsbt1->clk);
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return 0;
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}
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static const struct of_device_id dw_spi_bt1_of_match[] = {
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{ .compatible = "baikal,bt1-ssi", .data = dw_spi_bt1_std_init},
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{ .compatible = "baikal,bt1-sys-ssi", .data = dw_spi_bt1_sys_init},
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{ }
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};
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MODULE_DEVICE_TABLE(of, dw_spi_bt1_of_match);
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static struct platform_driver dw_spi_bt1_driver = {
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.probe = dw_spi_bt1_probe,
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.remove = dw_spi_bt1_remove,
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.driver = {
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.name = "bt1-sys-ssi",
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.of_match_table = dw_spi_bt1_of_match,
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},
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};
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module_platform_driver(dw_spi_bt1_driver);
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MODULE_AUTHOR("Serge Semin <Sergey.Semin@baikalelectronics.ru>");
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MODULE_DESCRIPTION("Baikal-T1 System Boot SPI Controller driver");
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(SPI_DW_CORE);
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