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b0c3d9354d
In preparation of adding support for a new bus type, separate the core spi-altera code from the platform driver code. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Link: https://lore.kernel.org/r/20210416165720.554144-2-matthew.gerlach@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
223 lines
5.0 KiB
C
223 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Altera SPI driver
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*
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* Copyright (C) 2008 Thomas Chou <thomas@wytron.com.tw>
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*
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* Based on spi_s3c24xx.c, which is:
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* Copyright (c) 2006 Ben Dooks
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*/
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/altera.h>
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#include <linux/spi/spi.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#define DRV_NAME "spi_altera"
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#define ALTERA_SPI_RXDATA 0
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#define ALTERA_SPI_TXDATA 4
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#define ALTERA_SPI_STATUS 8
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#define ALTERA_SPI_CONTROL 12
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#define ALTERA_SPI_SLAVE_SEL 20
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#define ALTERA_SPI_STATUS_ROE_MSK 0x8
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#define ALTERA_SPI_STATUS_TOE_MSK 0x10
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#define ALTERA_SPI_STATUS_TMT_MSK 0x20
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#define ALTERA_SPI_STATUS_TRDY_MSK 0x40
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#define ALTERA_SPI_STATUS_RRDY_MSK 0x80
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#define ALTERA_SPI_STATUS_E_MSK 0x100
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#define ALTERA_SPI_CONTROL_IROE_MSK 0x8
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#define ALTERA_SPI_CONTROL_ITOE_MSK 0x10
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#define ALTERA_SPI_CONTROL_ITRDY_MSK 0x40
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#define ALTERA_SPI_CONTROL_IRRDY_MSK 0x80
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#define ALTERA_SPI_CONTROL_IE_MSK 0x100
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#define ALTERA_SPI_CONTROL_SSO_MSK 0x400
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static int altr_spi_writel(struct altera_spi *hw, unsigned int reg,
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unsigned int val)
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{
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int ret;
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ret = regmap_write(hw->regmap, hw->regoff + reg, val);
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if (ret)
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dev_err(hw->dev, "fail to write reg 0x%x val 0x%x: %d\n",
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reg, val, ret);
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return ret;
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}
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static int altr_spi_readl(struct altera_spi *hw, unsigned int reg,
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unsigned int *val)
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{
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int ret;
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ret = regmap_read(hw->regmap, hw->regoff + reg, val);
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if (ret)
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dev_err(hw->dev, "fail to read reg 0x%x: %d\n", reg, ret);
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return ret;
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}
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static inline struct altera_spi *altera_spi_to_hw(struct spi_device *sdev)
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{
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return spi_master_get_devdata(sdev->master);
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}
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static void altera_spi_set_cs(struct spi_device *spi, bool is_high)
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{
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struct altera_spi *hw = altera_spi_to_hw(spi);
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if (is_high) {
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hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK;
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altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
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altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL, 0);
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} else {
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altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL,
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BIT(spi->chip_select));
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hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
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altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
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}
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}
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static void altera_spi_tx_word(struct altera_spi *hw)
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{
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unsigned int txd = 0;
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if (hw->tx) {
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switch (hw->bytes_per_word) {
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case 1:
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txd = hw->tx[hw->count];
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break;
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case 2:
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txd = (hw->tx[hw->count * 2]
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| (hw->tx[hw->count * 2 + 1] << 8));
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break;
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case 4:
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txd = (hw->tx[hw->count * 4]
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| (hw->tx[hw->count * 4 + 1] << 8)
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| (hw->tx[hw->count * 4 + 2] << 16)
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| (hw->tx[hw->count * 4 + 3] << 24));
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break;
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}
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}
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altr_spi_writel(hw, ALTERA_SPI_TXDATA, txd);
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}
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static void altera_spi_rx_word(struct altera_spi *hw)
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{
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unsigned int rxd;
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altr_spi_readl(hw, ALTERA_SPI_RXDATA, &rxd);
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if (hw->rx) {
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switch (hw->bytes_per_word) {
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case 1:
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hw->rx[hw->count] = rxd;
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break;
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case 2:
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hw->rx[hw->count * 2] = rxd;
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hw->rx[hw->count * 2 + 1] = rxd >> 8;
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break;
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case 4:
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hw->rx[hw->count * 4] = rxd;
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hw->rx[hw->count * 4 + 1] = rxd >> 8;
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hw->rx[hw->count * 4 + 2] = rxd >> 16;
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hw->rx[hw->count * 4 + 3] = rxd >> 24;
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break;
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}
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}
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hw->count++;
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}
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static int altera_spi_txrx(struct spi_master *master,
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struct spi_device *spi, struct spi_transfer *t)
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{
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struct altera_spi *hw = spi_master_get_devdata(master);
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u32 val;
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hw->tx = t->tx_buf;
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hw->rx = t->rx_buf;
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hw->count = 0;
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hw->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
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hw->len = t->len / hw->bytes_per_word;
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if (hw->irq >= 0) {
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/* enable receive interrupt */
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hw->imr |= ALTERA_SPI_CONTROL_IRRDY_MSK;
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altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
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/* send the first byte */
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altera_spi_tx_word(hw);
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return 1;
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}
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while (hw->count < hw->len) {
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altera_spi_tx_word(hw);
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for (;;) {
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altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
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if (val & ALTERA_SPI_STATUS_RRDY_MSK)
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break;
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cpu_relax();
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}
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altera_spi_rx_word(hw);
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}
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spi_finalize_current_transfer(master);
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return 0;
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}
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irqreturn_t altera_spi_irq(int irq, void *dev)
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{
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struct spi_master *master = dev;
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struct altera_spi *hw = spi_master_get_devdata(master);
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altera_spi_rx_word(hw);
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if (hw->count < hw->len) {
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altera_spi_tx_word(hw);
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} else {
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/* disable receive interrupt */
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hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK;
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altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
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spi_finalize_current_transfer(master);
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}
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(altera_spi_irq);
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void altera_spi_init_master(struct spi_master *master)
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{
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struct altera_spi *hw = spi_master_get_devdata(master);
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u32 val;
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master->transfer_one = altera_spi_txrx;
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master->set_cs = altera_spi_set_cs;
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/* program defaults into the registers */
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hw->imr = 0; /* disable spi interrupts */
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altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
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altr_spi_writel(hw, ALTERA_SPI_STATUS, 0); /* clear status reg */
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altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
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if (val & ALTERA_SPI_STATUS_RRDY_MSK)
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altr_spi_readl(hw, ALTERA_SPI_RXDATA, &val); /* flush rxdata */
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}
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EXPORT_SYMBOL_GPL(altera_spi_init_master);
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MODULE_LICENSE("GPL");
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