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faaa222221
pwmchip_remove() returns always 0. Don't use the value to make it possible to eventually change the function to return void. Also the driver core ignores the return value of pwm_omap_dmtimer_remove() and considers the device removed anyhow. So returning early results in a resource leak. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
483 lines
13 KiB
C
483 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
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* Copyright (c) 2012 NeilBrown <neilb@suse.de>
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* Heavily based on earlier code which is:
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* Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
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*
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* Also based on pwm-samsung.c
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*
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* Description:
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* This file is the core OMAP support for the generic, Linux
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* PWM driver / controller, using the OMAP's dual-mode timers
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* with a timer counter that goes up. When it overflows it gets
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* reloaded with the load value and the pwm output goes up.
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* When counter matches with match register, the output goes down.
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* Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
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*
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* Limitations:
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* - When PWM is stopped, timer counter gets stopped immediately. This
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* doesn't allow the current PWM period to complete and stops abruptly.
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* - When PWM is running and changing both duty cycle and period,
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* we cannot prevent in software that the output might produce
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* a period with mixed settings. Especially when period/duty_cyle
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* is updated while the pwm pin is high, current pwm period/duty_cycle
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* can get updated as below based on the current timer counter:
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* - period for current cycle = current_period + new period
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* - duty_cycle for current period = current period + new duty_cycle.
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* - PWM OMAP DM timer cannot change the polarity when pwm is active. When
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* user requests a change in polarity when in active state:
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* - PWM is stopped abruptly(without completing the current cycle)
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* - Polarity is changed
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* - A fresh cycle is started.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <clocksource/timer-ti-dm.h>
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#include <linux/platform_data/dmtimer-omap.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/time.h>
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#define DM_TIMER_LOAD_MIN 0xfffffffe
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#define DM_TIMER_MAX 0xffffffff
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/**
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* struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
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* corresponding to omap dmtimer.
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* @chip: PWM chip structure representing PWM controller
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* @mutex: Mutex to protect pwm apply state
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* @dm_timer: Pointer to omap dm timer.
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* @pdata: Pointer to omap dm timer ops.
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* @dm_timer_pdev: Pointer to omap dm timer platform device
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*/
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struct pwm_omap_dmtimer_chip {
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struct pwm_chip chip;
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/* Mutex to protect pwm apply state */
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struct mutex mutex;
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struct omap_dm_timer *dm_timer;
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const struct omap_dm_timer_ops *pdata;
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struct platform_device *dm_timer_pdev;
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};
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static inline struct pwm_omap_dmtimer_chip *
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to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
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}
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/**
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* pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
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* @clk_rate: pwm timer clock rate
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* @ns: time frame in nano seconds.
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*
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* Return number of clock cycles in a given period(ins ns).
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*/
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static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
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{
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return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
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}
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/**
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* pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
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* @omap: Pointer to pwm omap dm timer chip
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*/
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static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
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{
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/*
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* According to OMAP 4 TRM section 22.2.4.10 the counter should be
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* started at 0xFFFFFFFE when overflow and match is used to ensure
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* that the PWM line is toggled on the first event.
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*
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* Note that omap_dm_timer_enable/disable is for register access and
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* not the timer counter itself.
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*/
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omap->pdata->enable(omap->dm_timer);
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omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
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omap->pdata->disable(omap->dm_timer);
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omap->pdata->start(omap->dm_timer);
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}
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/**
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* pwm_omap_dmtimer_is_enabled() - Detect if the pwm is enabled.
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* @omap: Pointer to pwm omap dm timer chip
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*
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* Return true if pwm is enabled else false.
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*/
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static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
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{
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u32 status;
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status = omap->pdata->get_pwm_status(omap->dm_timer);
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return !!(status & OMAP_TIMER_CTRL_ST);
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}
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/**
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* pwm_omap_dmtimer_polarity() - Detect the polarity of pwm.
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* @omap: Pointer to pwm omap dm timer chip
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*
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* Return the polarity of pwm.
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*/
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static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
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{
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u32 status;
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status = omap->pdata->get_pwm_status(omap->dm_timer);
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return !!(status & OMAP_TIMER_CTRL_SCPWM);
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}
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/**
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* pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
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* @chip: Pointer to PWM controller
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* @pwm: Pointer to PWM channel
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* @duty_ns: New duty cycle in nano seconds
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* @period_ns: New period in nano seconds
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*
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* Return 0 if successfully changed the period/duty_cycle else appropriate
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* error.
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*/
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static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
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struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
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u32 period_cycles, duty_cycles;
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u32 load_value, match_value;
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unsigned long clk_rate;
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struct clk *fclk;
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dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
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duty_ns, period_ns);
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if (duty_ns == pwm_get_duty_cycle(pwm) &&
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period_ns == pwm_get_period(pwm))
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return 0;
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fclk = omap->pdata->get_fclk(omap->dm_timer);
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if (!fclk) {
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dev_err(chip->dev, "invalid pmtimer fclk\n");
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return -EINVAL;
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}
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clk_rate = clk_get_rate(fclk);
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if (!clk_rate) {
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dev_err(chip->dev, "invalid pmtimer fclk rate\n");
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return -EINVAL;
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}
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dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
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/*
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* Calculate the appropriate load and match values based on the
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* specified period and duty cycle. The load value determines the
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* period time and the match value determines the duty time.
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*
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* The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
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* Similarly, the active time lasts (match_value-load_value+1) cycles.
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* The non-active time is the remainder: (DM_TIMER_MAX-match_value)
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* clock cycles.
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*
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* NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
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*
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* References:
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* OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
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* AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
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*/
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period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
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duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
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if (period_cycles < 2) {
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dev_info(chip->dev,
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"period %d ns too short for clock rate %lu Hz\n",
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period_ns, clk_rate);
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return -EINVAL;
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}
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if (duty_cycles < 1) {
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dev_dbg(chip->dev,
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"duty cycle %d ns is too short for clock rate %lu Hz\n",
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duty_ns, clk_rate);
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dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
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duty_cycles = 1;
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} else if (duty_cycles >= period_cycles) {
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dev_dbg(chip->dev,
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"duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
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duty_ns, period_ns, clk_rate);
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dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
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duty_cycles = period_cycles - 1;
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}
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dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
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DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
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clk_rate),
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DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
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clk_rate));
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load_value = (DM_TIMER_MAX - period_cycles) + 1;
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match_value = load_value + duty_cycles - 1;
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omap->pdata->set_load(omap->dm_timer, load_value);
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omap->pdata->set_match(omap->dm_timer, true, match_value);
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dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
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load_value, load_value, match_value, match_value);
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return 0;
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}
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/**
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* pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
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* @chip: Pointer to PWM controller
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* @pwm: Pointer to PWM channel
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* @polarity: New pwm polarity to be set
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*/
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static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
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bool enabled;
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/* Disable the PWM before changing the polarity. */
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enabled = pwm_omap_dmtimer_is_enabled(omap);
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if (enabled)
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omap->pdata->stop(omap->dm_timer);
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omap->pdata->set_pwm(omap->dm_timer,
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polarity == PWM_POLARITY_INVERSED,
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true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
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true);
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if (enabled)
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pwm_omap_dmtimer_start(omap);
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}
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/**
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* pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
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* @chip: Pointer to PWM controller
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* @pwm: Pointer to PWM channel
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* @state: New state to apply
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*
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* Return 0 if successfully changed the state else appropriate error.
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*/
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static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
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struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
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int ret = 0;
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mutex_lock(&omap->mutex);
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if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
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omap->pdata->stop(omap->dm_timer);
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goto unlock_mutex;
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}
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if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
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pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);
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ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
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state->period);
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if (ret)
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goto unlock_mutex;
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if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
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omap->pdata->set_pwm(omap->dm_timer,
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state->polarity == PWM_POLARITY_INVERSED,
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true,
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OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
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true);
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pwm_omap_dmtimer_start(omap);
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}
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unlock_mutex:
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mutex_unlock(&omap->mutex);
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return ret;
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}
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static const struct pwm_ops pwm_omap_dmtimer_ops = {
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.apply = pwm_omap_dmtimer_apply,
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.owner = THIS_MODULE,
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};
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static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct dmtimer_platform_data *timer_pdata;
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const struct omap_dm_timer_ops *pdata;
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struct platform_device *timer_pdev;
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struct pwm_omap_dmtimer_chip *omap;
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struct omap_dm_timer *dm_timer;
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struct device_node *timer;
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int ret = 0;
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u32 v;
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timer = of_parse_phandle(np, "ti,timers", 0);
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if (!timer)
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return -ENODEV;
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timer_pdev = of_find_device_by_node(timer);
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if (!timer_pdev) {
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dev_err(&pdev->dev, "Unable to find Timer pdev\n");
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ret = -ENODEV;
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goto err_find_timer_pdev;
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}
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timer_pdata = dev_get_platdata(&timer_pdev->dev);
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if (!timer_pdata) {
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dev_dbg(&pdev->dev,
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"dmtimer pdata structure NULL, deferring probe\n");
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ret = -EPROBE_DEFER;
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goto err_platdata;
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}
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pdata = timer_pdata->timer_ops;
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if (!pdata || !pdata->request_by_node ||
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!pdata->free ||
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!pdata->enable ||
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!pdata->disable ||
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!pdata->get_fclk ||
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!pdata->start ||
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!pdata->stop ||
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!pdata->set_load ||
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!pdata->set_match ||
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!pdata->set_pwm ||
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!pdata->get_pwm_status ||
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!pdata->set_prescaler ||
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!pdata->write_counter) {
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dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
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ret = -EINVAL;
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goto err_platdata;
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}
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if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
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dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
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ret = -ENODEV;
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goto err_timer_property;
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}
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dm_timer = pdata->request_by_node(timer);
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if (!dm_timer) {
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ret = -EPROBE_DEFER;
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goto err_request_timer;
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}
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omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
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if (!omap) {
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ret = -ENOMEM;
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goto err_alloc_omap;
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}
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omap->pdata = pdata;
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omap->dm_timer = dm_timer;
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omap->dm_timer_pdev = timer_pdev;
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/*
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* Ensure that the timer is stopped before we allow PWM core to call
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* pwm_enable.
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*/
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if (pm_runtime_active(&omap->dm_timer_pdev->dev))
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omap->pdata->stop(omap->dm_timer);
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if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
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omap->pdata->set_prescaler(omap->dm_timer, v);
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/* setup dmtimer clock source */
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if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
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omap->pdata->set_source(omap->dm_timer, v);
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omap->chip.dev = &pdev->dev;
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omap->chip.ops = &pwm_omap_dmtimer_ops;
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omap->chip.npwm = 1;
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mutex_init(&omap->mutex);
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ret = pwmchip_add(&omap->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to register PWM\n");
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goto err_pwmchip_add;
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}
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of_node_put(timer);
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platform_set_drvdata(pdev, omap);
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return 0;
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err_pwmchip_add:
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/*
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* *omap is allocated using devm_kzalloc,
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* so no free necessary here
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*/
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err_alloc_omap:
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pdata->free(dm_timer);
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err_request_timer:
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err_timer_property:
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err_platdata:
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put_device(&timer_pdev->dev);
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err_find_timer_pdev:
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of_node_put(timer);
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return ret;
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}
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static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
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{
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struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
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pwmchip_remove(&omap->chip);
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if (pm_runtime_active(&omap->dm_timer_pdev->dev))
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omap->pdata->stop(omap->dm_timer);
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omap->pdata->free(omap->dm_timer);
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put_device(&omap->dm_timer_pdev->dev);
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mutex_destroy(&omap->mutex);
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return 0;
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}
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static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
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{.compatible = "ti,omap-dmtimer-pwm"},
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{}
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};
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MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
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static struct platform_driver pwm_omap_dmtimer_driver = {
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.driver = {
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.name = "omap-dmtimer-pwm",
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.of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
|
|
},
|
|
.probe = pwm_omap_dmtimer_probe,
|
|
.remove = pwm_omap_dmtimer_remove,
|
|
};
|
|
module_platform_driver(pwm_omap_dmtimer_driver);
|
|
|
|
MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
|
|
MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
|
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");
|