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5ba3eb4bb3
This allows to drop the platform_driver's remove function. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
555 lines
13 KiB
C
555 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Freescale FlexTimer Module (FTM) PWM Driver
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*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/fsl/ftm.h>
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#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
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enum fsl_pwm_clk {
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FSL_PWM_CLK_SYS,
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FSL_PWM_CLK_FIX,
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FSL_PWM_CLK_EXT,
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FSL_PWM_CLK_CNTEN,
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FSL_PWM_CLK_MAX
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};
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struct fsl_ftm_soc {
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bool has_enable_bits;
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};
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struct fsl_pwm_periodcfg {
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enum fsl_pwm_clk clk_select;
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unsigned int clk_ps;
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unsigned int mod_period;
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};
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struct fsl_pwm_chip {
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struct pwm_chip chip;
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struct mutex lock;
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struct regmap *regmap;
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/* This value is valid iff a pwm is running */
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struct fsl_pwm_periodcfg period;
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struct clk *ipg_clk;
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struct clk *clk[FSL_PWM_CLK_MAX];
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const struct fsl_ftm_soc *soc;
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};
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static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct fsl_pwm_chip, chip);
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}
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static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
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{
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u32 val;
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regmap_read(fpc->regmap, FTM_FMS, &val);
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if (val & FTM_FMS_WPEN)
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regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
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FTM_MODE_WPDIS);
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}
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static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
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{
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regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
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}
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static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
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const struct fsl_pwm_periodcfg *b)
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{
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if (a->clk_select != b->clk_select)
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return false;
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if (a->clk_ps != b->clk_ps)
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return false;
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if (a->mod_period != b->mod_period)
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return false;
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return true;
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}
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static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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int ret;
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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ret = clk_prepare_enable(fpc->ipg_clk);
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if (!ret && fpc->soc->has_enable_bits) {
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mutex_lock(&fpc->lock);
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regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
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BIT(pwm->hwpwm + 16));
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mutex_unlock(&fpc->lock);
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}
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return ret;
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}
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static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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if (fpc->soc->has_enable_bits) {
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mutex_lock(&fpc->lock);
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regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16),
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0);
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mutex_unlock(&fpc->lock);
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}
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clk_disable_unprepare(fpc->ipg_clk);
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}
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static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
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unsigned int ticks)
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{
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unsigned long rate;
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unsigned long long exval;
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rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
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exval = ticks;
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exval *= 1000000000UL;
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do_div(exval, rate >> fpc->period.clk_ps);
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return exval;
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}
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static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
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unsigned int period_ns,
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enum fsl_pwm_clk index,
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struct fsl_pwm_periodcfg *periodcfg
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)
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{
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unsigned long long c;
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unsigned int ps;
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c = clk_get_rate(fpc->clk[index]);
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c = c * period_ns;
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do_div(c, 1000000000UL);
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if (c == 0)
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return false;
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for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
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if (c <= 0x10000) {
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periodcfg->clk_select = index;
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periodcfg->clk_ps = ps;
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periodcfg->mod_period = c - 1;
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return true;
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}
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}
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return false;
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}
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static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
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unsigned int period_ns,
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struct fsl_pwm_periodcfg *periodcfg)
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{
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enum fsl_pwm_clk m0, m1;
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unsigned long fix_rate, ext_rate;
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bool ret;
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ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
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periodcfg);
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if (ret)
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return true;
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fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
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ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
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if (fix_rate > ext_rate) {
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m0 = FSL_PWM_CLK_FIX;
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m1 = FSL_PWM_CLK_EXT;
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} else {
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m0 = FSL_PWM_CLK_EXT;
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m1 = FSL_PWM_CLK_FIX;
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}
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ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
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if (ret)
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return true;
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return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
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}
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static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
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unsigned int duty_ns)
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{
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unsigned long long duty;
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unsigned int period = fpc->period.mod_period + 1;
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unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
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duty = (unsigned long long)duty_ns * period;
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do_div(duty, period_ns);
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return (unsigned int)duty;
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}
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static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
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struct pwm_device *pwm)
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{
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u32 val;
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regmap_read(fpc->regmap, FTM_OUTMASK, &val);
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if (~val & 0xFF)
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return true;
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else
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return false;
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}
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static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
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struct pwm_device *pwm)
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{
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u32 val;
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regmap_read(fpc->regmap, FTM_OUTMASK, &val);
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if (~(val | BIT(pwm->hwpwm)) & 0xFF)
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return true;
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else
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return false;
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}
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static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
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struct pwm_device *pwm,
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const struct pwm_state *newstate)
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{
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unsigned int duty;
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u32 reg_polarity;
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struct fsl_pwm_periodcfg periodcfg;
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bool do_write_period = false;
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if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
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dev_err(fpc->chip.dev, "failed to calculate new period\n");
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return -EINVAL;
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}
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if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
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do_write_period = true;
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/*
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* The Freescale FTM controller supports only a single period for
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* all PWM channels, therefore verify if the newly computed period
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* is different than the current period being used. In such case
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* we allow to change the period only if no other pwm is running.
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*/
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else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
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if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
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dev_err(fpc->chip.dev,
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"Cannot change period for PWM %u, disable other PWMs first\n",
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pwm->hwpwm);
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return -EBUSY;
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}
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if (fpc->period.clk_select != periodcfg.clk_select) {
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int ret;
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enum fsl_pwm_clk oldclk = fpc->period.clk_select;
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enum fsl_pwm_clk newclk = periodcfg.clk_select;
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ret = clk_prepare_enable(fpc->clk[newclk]);
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if (ret)
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return ret;
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clk_disable_unprepare(fpc->clk[oldclk]);
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}
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do_write_period = true;
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}
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ftm_clear_write_protection(fpc);
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if (do_write_period) {
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regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
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FTM_SC_CLK(periodcfg.clk_select));
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regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
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periodcfg.clk_ps);
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regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
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fpc->period = periodcfg;
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}
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duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
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regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
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FTM_CSC_MSB | FTM_CSC_ELSB);
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regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
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reg_polarity = 0;
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if (newstate->polarity == PWM_POLARITY_INVERSED)
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reg_polarity = BIT(pwm->hwpwm);
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regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
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ftm_set_write_protection(fpc);
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return 0;
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}
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static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *newstate)
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{
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
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struct pwm_state *oldstate = &pwm->state;
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int ret = 0;
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/*
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* oldstate to newstate : action
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*
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* disabled to disabled : ignore
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* enabled to disabled : disable
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* enabled to enabled : update settings
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* disabled to enabled : update settings + enable
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*/
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mutex_lock(&fpc->lock);
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if (!newstate->enabled) {
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if (oldstate->enabled) {
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regmap_update_bits(fpc->regmap, FTM_OUTMASK,
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BIT(pwm->hwpwm), BIT(pwm->hwpwm));
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clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
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clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
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}
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goto end_mutex;
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}
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ret = fsl_pwm_apply_config(fpc, pwm, newstate);
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if (ret)
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goto end_mutex;
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/* check if need to enable */
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if (!oldstate->enabled) {
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ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
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if (ret)
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goto end_mutex;
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ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
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if (ret) {
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clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
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goto end_mutex;
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}
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regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
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0);
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}
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end_mutex:
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mutex_unlock(&fpc->lock);
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return ret;
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}
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static const struct pwm_ops fsl_pwm_ops = {
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.request = fsl_pwm_request,
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.free = fsl_pwm_free,
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.apply = fsl_pwm_apply,
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.owner = THIS_MODULE,
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};
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static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
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{
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int ret;
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ret = clk_prepare_enable(fpc->ipg_clk);
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if (ret)
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return ret;
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regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
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regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
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regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
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clk_disable_unprepare(fpc->ipg_clk);
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return 0;
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}
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static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case FTM_FMS:
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case FTM_MODE:
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case FTM_CNT:
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return true;
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}
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return false;
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}
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static const struct regmap_config fsl_pwm_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = FTM_PWMLOAD,
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.volatile_reg = fsl_pwm_volatile_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static int fsl_pwm_probe(struct platform_device *pdev)
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{
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struct fsl_pwm_chip *fpc;
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void __iomem *base;
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int ret;
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fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
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if (!fpc)
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return -ENOMEM;
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mutex_init(&fpc->lock);
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fpc->soc = of_device_get_match_data(&pdev->dev);
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fpc->chip.dev = &pdev->dev;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
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&fsl_pwm_regmap_config);
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if (IS_ERR(fpc->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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return PTR_ERR(fpc->regmap);
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}
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fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
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dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
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}
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fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
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fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
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fpc->clk[FSL_PWM_CLK_CNTEN] =
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devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
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if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
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return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
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/*
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* ipg_clk is the interface clock for the IP. If not provided, use the
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* ftm_sys clock as the default.
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*/
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fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(fpc->ipg_clk))
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fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
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fpc->chip.ops = &fsl_pwm_ops;
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fpc->chip.npwm = 8;
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ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, fpc);
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return fsl_pwm_init(fpc);
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}
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#ifdef CONFIG_PM_SLEEP
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static int fsl_pwm_suspend(struct device *dev)
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{
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struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
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int i;
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regcache_cache_only(fpc->regmap, true);
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regcache_mark_dirty(fpc->regmap);
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for (i = 0; i < fpc->chip.npwm; i++) {
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struct pwm_device *pwm = &fpc->chip.pwms[i];
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if (!test_bit(PWMF_REQUESTED, &pwm->flags))
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continue;
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clk_disable_unprepare(fpc->ipg_clk);
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if (!pwm_is_enabled(pwm))
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continue;
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clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
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clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
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}
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return 0;
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}
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static int fsl_pwm_resume(struct device *dev)
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{
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struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
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int i;
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|
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for (i = 0; i < fpc->chip.npwm; i++) {
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struct pwm_device *pwm = &fpc->chip.pwms[i];
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|
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if (!test_bit(PWMF_REQUESTED, &pwm->flags))
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continue;
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|
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clk_prepare_enable(fpc->ipg_clk);
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|
|
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if (!pwm_is_enabled(pwm))
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continue;
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|
|
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clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
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clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
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}
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|
|
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/* restore all registers from cache */
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regcache_cache_only(fpc->regmap, false);
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regcache_sync(fpc->regmap);
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|
|
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return 0;
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}
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|
#endif
|
|
|
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static const struct dev_pm_ops fsl_pwm_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
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|
};
|
|
|
|
static const struct fsl_ftm_soc vf610_ftm_pwm = {
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|
.has_enable_bits = false,
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|
};
|
|
|
|
static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
|
|
.has_enable_bits = true,
|
|
};
|
|
|
|
static const struct of_device_id fsl_pwm_dt_ids[] = {
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|
{ .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
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|
{ .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
|
|
|
|
static struct platform_driver fsl_pwm_driver = {
|
|
.driver = {
|
|
.name = "fsl-ftm-pwm",
|
|
.of_match_table = fsl_pwm_dt_ids,
|
|
.pm = &fsl_pwm_pm_ops,
|
|
},
|
|
.probe = fsl_pwm_probe,
|
|
};
|
|
module_platform_driver(fsl_pwm_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
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|
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
|
|
MODULE_ALIAS("platform:fsl-ftm-pwm");
|
|
MODULE_LICENSE("GPL");
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