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e6b142060b
Many DSDTs for Kaby Lake and Kaby Lake Refresh models contain a _SB.PCI0.GEXP ACPI Device node describing an I2C attached PCA953x GPIO expander. This seems to be something which is copy and pasted from the DSDT from some reference design since this ACPI Device is present even on models where no such GPIO expander is used at all, such as on the Microsoft Surface Go & Go 2. This ACPI Device is a problem because it contains a SystemMemory OperationRegion which covers the MMIO for the I2C4 I2C controller. This causes the MFD cell for the I2C4 controller to not be instantiated due to a resource conflict, requiring the use of acpi_enforce_resources=lax to work around this. I have done an extensive analysis of all the ACPI tables on the Microsoft Surface Go and the _SB.PCI0.GEXP ACPI Device's methods are not used by any code in the ACPI tables, neither are any of them directly called by any Linux kernel code. This is unsurprising since running i2cdetect on the I2C4 bus shows that there is no GPIO expander chip present on these devices at all. This commit adds a PCI subsystem vendor:device table listing PCI devices where it is known to be safe to ignore resource conflicts with ACPI declared SystemMemory regions. This makes the I2C4 bus work out of the box on the Microsoft Surface Go & Go 2, which is necessary for the cameras on these devices to work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211203115108.89661-1-hdegoede@redhat.com
546 lines
13 KiB
C
546 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Sunrisepoint LPSS core support.
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*
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* Copyright (C) 2015, Intel Corporation
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*
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* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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* Mika Westerberg <mika.westerberg@linux.intel.com>
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* Heikki Krogerus <heikki.krogerus@linux.intel.com>
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* Jarkko Nikula <jarkko.nikula@linux.intel.com>
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/debugfs.h>
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#include <linux/idr.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mfd/core.h>
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#include <linux/pm_qos.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include <linux/seq_file.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dma/idma64.h>
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#include "intel-lpss.h"
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#define LPSS_DEV_OFFSET 0x000
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#define LPSS_DEV_SIZE 0x200
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#define LPSS_PRIV_OFFSET 0x200
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#define LPSS_PRIV_SIZE 0x100
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#define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
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#define LPSS_IDMA64_OFFSET 0x800
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#define LPSS_IDMA64_SIZE 0x800
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/* Offsets from lpss->priv */
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#define LPSS_PRIV_RESETS 0x04
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#define LPSS_PRIV_RESETS_IDMA BIT(2)
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#define LPSS_PRIV_RESETS_FUNC 0x3
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#define LPSS_PRIV_ACTIVELTR 0x10
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#define LPSS_PRIV_IDLELTR 0x14
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#define LPSS_PRIV_LTR_REQ BIT(15)
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#define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)
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#define LPSS_PRIV_LTR_SCALE_1US (2 << 10)
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#define LPSS_PRIV_LTR_SCALE_32US (3 << 10)
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#define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)
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#define LPSS_PRIV_SSP_REG 0x20
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#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
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#define LPSS_PRIV_REMAP_ADDR 0x40
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#define LPSS_PRIV_CAPS 0xfc
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#define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
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#define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)
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#define LPSS_PRIV_CAPS_TYPE_SHIFT 4
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/* This matches the type field in CAPS register */
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enum intel_lpss_dev_type {
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LPSS_DEV_I2C = 0,
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LPSS_DEV_UART,
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LPSS_DEV_SPI,
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};
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struct intel_lpss {
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const struct intel_lpss_platform_info *info;
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enum intel_lpss_dev_type type;
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struct clk *clk;
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struct clk_lookup *clock;
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struct mfd_cell *cell;
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struct device *dev;
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void __iomem *priv;
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u32 priv_ctx[LPSS_PRIV_REG_COUNT];
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int devid;
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u32 caps;
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u32 active_ltr;
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u32 idle_ltr;
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struct dentry *debugfs;
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};
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static const struct resource intel_lpss_dev_resources[] = {
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DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
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DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
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DEFINE_RES_IRQ(0),
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};
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static const struct resource intel_lpss_idma64_resources[] = {
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DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
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DEFINE_RES_IRQ(0),
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};
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/*
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* Cells needs to be ordered so that the iDMA is created first. This is
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* because we need to be sure the DMA is available when the host controller
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* driver is probed.
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*/
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static const struct mfd_cell intel_lpss_idma64_cell = {
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.name = LPSS_IDMA64_DRIVER_NAME,
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.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
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.resources = intel_lpss_idma64_resources,
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};
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static const struct mfd_cell intel_lpss_i2c_cell = {
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.name = "i2c_designware",
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.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
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.resources = intel_lpss_dev_resources,
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};
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static const struct mfd_cell intel_lpss_uart_cell = {
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.name = "dw-apb-uart",
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.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
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.resources = intel_lpss_dev_resources,
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};
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static const struct mfd_cell intel_lpss_spi_cell = {
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.name = "pxa2xx-spi",
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.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
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.resources = intel_lpss_dev_resources,
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};
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static DEFINE_IDA(intel_lpss_devid_ida);
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static struct dentry *intel_lpss_debugfs;
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static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
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{
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lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
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lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
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}
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static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
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{
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struct dentry *dir;
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dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
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if (IS_ERR(dir))
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return PTR_ERR(dir);
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/* Cache the values into lpss structure */
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intel_lpss_cache_ltr(lpss);
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debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
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debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
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debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
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lpss->debugfs = dir;
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return 0;
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}
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static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
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{
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debugfs_remove_recursive(lpss->debugfs);
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}
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static void intel_lpss_ltr_set(struct device *dev, s32 val)
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{
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struct intel_lpss *lpss = dev_get_drvdata(dev);
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u32 ltr;
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/*
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* Program latency tolerance (LTR) accordingly what has been asked
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* by the PM QoS layer or disable it in case we were passed
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* negative value or PM_QOS_LATENCY_ANY.
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*/
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ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
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if (val == PM_QOS_LATENCY_ANY || val < 0) {
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ltr &= ~LPSS_PRIV_LTR_REQ;
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} else {
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ltr |= LPSS_PRIV_LTR_REQ;
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ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
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ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
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if (val > LPSS_PRIV_LTR_VALUE_MASK)
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ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
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else
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ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
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}
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if (ltr == lpss->active_ltr)
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return;
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writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
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writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
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/* Cache the values into lpss structure */
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intel_lpss_cache_ltr(lpss);
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}
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static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
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{
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lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
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dev_pm_qos_expose_latency_tolerance(lpss->dev);
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}
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static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
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{
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dev_pm_qos_hide_latency_tolerance(lpss->dev);
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lpss->dev->power.set_latency_tolerance = NULL;
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}
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static int intel_lpss_assign_devs(struct intel_lpss *lpss)
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{
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const struct mfd_cell *cell;
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unsigned int type;
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type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
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type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
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switch (type) {
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case LPSS_DEV_I2C:
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cell = &intel_lpss_i2c_cell;
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break;
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case LPSS_DEV_UART:
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cell = &intel_lpss_uart_cell;
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break;
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case LPSS_DEV_SPI:
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cell = &intel_lpss_spi_cell;
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break;
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default:
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return -ENODEV;
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}
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lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
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if (!lpss->cell)
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return -ENOMEM;
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lpss->type = type;
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return 0;
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}
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static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
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{
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return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
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}
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static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
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{
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resource_size_t addr = lpss->info->mem->start;
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lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
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}
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static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
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{
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u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
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/* Bring out the device from reset */
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writel(value, lpss->priv + LPSS_PRIV_RESETS);
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}
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static void intel_lpss_init_dev(const struct intel_lpss *lpss)
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{
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u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
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/* Set the device in reset state */
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writel(0, lpss->priv + LPSS_PRIV_RESETS);
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intel_lpss_deassert_reset(lpss);
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intel_lpss_set_remap_addr(lpss);
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if (!intel_lpss_has_idma(lpss))
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return;
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/* Make sure that SPI multiblock DMA transfers are re-enabled */
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if (lpss->type == LPSS_DEV_SPI)
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writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
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}
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static void intel_lpss_unregister_clock_tree(struct clk *clk)
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{
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struct clk *parent;
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while (clk) {
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parent = clk_get_parent(clk);
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clk_unregister(clk);
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clk = parent;
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}
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}
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static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
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const char *devname,
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struct clk **clk)
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{
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char name[32];
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struct clk *tmp = *clk;
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snprintf(name, sizeof(name), "%s-enable", devname);
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tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
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lpss->priv, 0, 0, NULL);
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if (IS_ERR(tmp))
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return PTR_ERR(tmp);
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snprintf(name, sizeof(name), "%s-div", devname);
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tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
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CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
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lpss->priv, 1, 15, 16, 15, 0,
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NULL);
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if (IS_ERR(tmp))
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return PTR_ERR(tmp);
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*clk = tmp;
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snprintf(name, sizeof(name), "%s-update", devname);
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tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
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CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
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if (IS_ERR(tmp))
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return PTR_ERR(tmp);
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*clk = tmp;
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return 0;
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}
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static int intel_lpss_register_clock(struct intel_lpss *lpss)
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{
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const struct mfd_cell *cell = lpss->cell;
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struct clk *clk;
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char devname[24];
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int ret;
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if (!lpss->info->clk_rate)
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return 0;
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/* Root clock */
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clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
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lpss->info->clk_rate);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
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/*
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* Support for clock divider only if it has some preset value.
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* Otherwise we assume that the divider is not used.
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*/
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if (lpss->type != LPSS_DEV_I2C) {
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ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
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if (ret)
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goto err_clk_register;
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}
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ret = -ENOMEM;
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/* Clock for the host controller */
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lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
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if (!lpss->clock)
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goto err_clk_register;
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lpss->clk = clk;
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return 0;
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err_clk_register:
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intel_lpss_unregister_clock_tree(clk);
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return ret;
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}
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static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
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{
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if (IS_ERR_OR_NULL(lpss->clk))
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return;
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clkdev_drop(lpss->clock);
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intel_lpss_unregister_clock_tree(lpss->clk);
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}
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int intel_lpss_probe(struct device *dev,
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const struct intel_lpss_platform_info *info)
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{
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struct intel_lpss *lpss;
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int ret;
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if (!info || !info->mem || info->irq <= 0)
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return -EINVAL;
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lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
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if (!lpss)
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return -ENOMEM;
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lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
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LPSS_PRIV_SIZE);
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if (!lpss->priv)
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return -ENOMEM;
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lpss->info = info;
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lpss->dev = dev;
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lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
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dev_set_drvdata(dev, lpss);
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ret = intel_lpss_assign_devs(lpss);
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if (ret)
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return ret;
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lpss->cell->swnode = info->swnode;
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lpss->cell->ignore_resource_conflicts = info->ignore_resource_conflicts;
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intel_lpss_init_dev(lpss);
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lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
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if (lpss->devid < 0)
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return lpss->devid;
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ret = intel_lpss_register_clock(lpss);
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if (ret)
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goto err_clk_register;
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intel_lpss_ltr_expose(lpss);
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ret = intel_lpss_debugfs_add(lpss);
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if (ret)
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dev_warn(dev, "Failed to create debugfs entries\n");
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if (intel_lpss_has_idma(lpss)) {
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ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
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1, info->mem, info->irq, NULL);
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if (ret)
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dev_warn(dev, "Failed to add %s, fallback to PIO\n",
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LPSS_IDMA64_DRIVER_NAME);
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}
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ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
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1, info->mem, info->irq, NULL);
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if (ret)
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goto err_remove_ltr;
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dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
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return 0;
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err_remove_ltr:
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intel_lpss_debugfs_remove(lpss);
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intel_lpss_ltr_hide(lpss);
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intel_lpss_unregister_clock(lpss);
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err_clk_register:
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ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
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return ret;
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}
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EXPORT_SYMBOL_GPL(intel_lpss_probe);
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void intel_lpss_remove(struct device *dev)
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{
|
|
struct intel_lpss *lpss = dev_get_drvdata(dev);
|
|
|
|
mfd_remove_devices(dev);
|
|
intel_lpss_debugfs_remove(lpss);
|
|
intel_lpss_ltr_hide(lpss);
|
|
intel_lpss_unregister_clock(lpss);
|
|
ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_lpss_remove);
|
|
|
|
static int resume_lpss_device(struct device *dev, void *data)
|
|
{
|
|
if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
|
|
pm_runtime_resume(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int intel_lpss_prepare(struct device *dev)
|
|
{
|
|
/*
|
|
* Resume both child devices before entering system sleep. This
|
|
* ensures that they are in proper state before they get suspended.
|
|
*/
|
|
device_for_each_child_reverse(dev, NULL, resume_lpss_device);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_lpss_prepare);
|
|
|
|
int intel_lpss_suspend(struct device *dev)
|
|
{
|
|
struct intel_lpss *lpss = dev_get_drvdata(dev);
|
|
unsigned int i;
|
|
|
|
/* Save device context */
|
|
for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
|
|
lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
|
|
|
|
/*
|
|
* If the device type is not UART, then put the controller into
|
|
* reset. UART cannot be put into reset since S3/S0ix fail when
|
|
* no_console_suspend flag is enabled.
|
|
*/
|
|
if (lpss->type != LPSS_DEV_UART)
|
|
writel(0, lpss->priv + LPSS_PRIV_RESETS);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_lpss_suspend);
|
|
|
|
int intel_lpss_resume(struct device *dev)
|
|
{
|
|
struct intel_lpss *lpss = dev_get_drvdata(dev);
|
|
unsigned int i;
|
|
|
|
intel_lpss_deassert_reset(lpss);
|
|
|
|
/* Restore device context */
|
|
for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
|
|
writel(lpss->priv_ctx[i], lpss->priv + i * 4);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(intel_lpss_resume);
|
|
|
|
static int __init intel_lpss_init(void)
|
|
{
|
|
intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
|
|
return 0;
|
|
}
|
|
module_init(intel_lpss_init);
|
|
|
|
static void __exit intel_lpss_exit(void)
|
|
{
|
|
ida_destroy(&intel_lpss_devid_ida);
|
|
debugfs_remove(intel_lpss_debugfs);
|
|
}
|
|
module_exit(intel_lpss_exit);
|
|
|
|
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
|
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
|
|
MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
|
|
MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
|
|
MODULE_DESCRIPTION("Intel LPSS core driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
/*
|
|
* Ensure the DMA driver is loaded before the host controller device appears,
|
|
* so that the host controller driver can request its DMA channels as early
|
|
* as possible.
|
|
*
|
|
* If the DMA module is not there that's OK as well.
|
|
*/
|
|
MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);
|