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6457f4cd78
Some sensors connected to Unisoc mailbox will send data very frequently. This makes channel 0 very busy and the messages from other remote cores not able to be handled as soon as possible. It's a trick (un-documented) from Unisoc ASIC designers to resolve this special requirement that an inbox assigned to one of the remote cores before was modified to be exposed to host cpu core. Then from host side, a supplementary inbox is added for transferring mass but not emergency messages from the remote cores, such as step counting sensor, with an independent FIFO and interrupt which is as same as channel 0. Meanwihle, inbox part of this channel is still kept for original remote core to use. Signed-off-by: Orson Zhai <orson.zhai@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
431 lines
12 KiB
C
431 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Spreadtrum mailbox driver
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*
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* Copyright (c) 2020 Spreadtrum Communications Inc.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#define SPRD_MBOX_ID 0x0
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#define SPRD_MBOX_MSG_LOW 0x4
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#define SPRD_MBOX_MSG_HIGH 0x8
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#define SPRD_MBOX_TRIGGER 0xc
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#define SPRD_MBOX_FIFO_RST 0x10
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#define SPRD_MBOX_FIFO_STS 0x14
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#define SPRD_MBOX_IRQ_STS 0x18
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#define SPRD_MBOX_IRQ_MSK 0x1c
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#define SPRD_MBOX_LOCK 0x20
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#define SPRD_MBOX_FIFO_DEPTH 0x24
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/* Bit and mask definition for inbox's SPRD_MBOX_FIFO_STS register */
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#define SPRD_INBOX_FIFO_DELIVER_MASK GENMASK(23, 16)
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#define SPRD_INBOX_FIFO_OVERLOW_MASK GENMASK(15, 8)
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#define SPRD_INBOX_FIFO_DELIVER_SHIFT 16
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#define SPRD_INBOX_FIFO_BUSY_MASK GENMASK(7, 0)
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/* Bit and mask definition for SPRD_MBOX_IRQ_STS register */
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#define SPRD_MBOX_IRQ_CLR BIT(0)
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/* Bit and mask definition for outbox's SPRD_MBOX_FIFO_STS register */
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#define SPRD_OUTBOX_FIFO_FULL BIT(2)
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#define SPRD_OUTBOX_FIFO_WR_SHIFT 16
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#define SPRD_OUTBOX_FIFO_RD_SHIFT 24
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#define SPRD_OUTBOX_FIFO_POS_MASK GENMASK(7, 0)
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/* Bit and mask definition for inbox's SPRD_MBOX_IRQ_MSK register */
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#define SPRD_INBOX_FIFO_BLOCK_IRQ BIT(0)
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#define SPRD_INBOX_FIFO_OVERFLOW_IRQ BIT(1)
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#define SPRD_INBOX_FIFO_DELIVER_IRQ BIT(2)
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#define SPRD_INBOX_FIFO_IRQ_MASK GENMASK(2, 0)
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/* Bit and mask definition for outbox's SPRD_MBOX_IRQ_MSK register */
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#define SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ BIT(0)
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#define SPRD_OUTBOX_FIFO_IRQ_MASK GENMASK(4, 0)
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#define SPRD_OUTBOX_BASE_SPAN 0x1000
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#define SPRD_MBOX_CHAN_MAX 8
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#define SPRD_SUPP_INBOX_ID_SC9863A 7
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struct sprd_mbox_priv {
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struct mbox_controller mbox;
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struct device *dev;
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void __iomem *inbox_base;
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void __iomem *outbox_base;
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/* Base register address for supplementary outbox */
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void __iomem *supp_base;
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struct clk *clk;
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u32 outbox_fifo_depth;
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struct mutex lock;
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u32 refcnt;
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struct mbox_chan chan[SPRD_MBOX_CHAN_MAX];
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};
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static struct sprd_mbox_priv *to_sprd_mbox_priv(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct sprd_mbox_priv, mbox);
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}
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static u32 sprd_mbox_get_fifo_len(struct sprd_mbox_priv *priv, u32 fifo_sts)
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{
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u32 wr_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_WR_SHIFT) &
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SPRD_OUTBOX_FIFO_POS_MASK;
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u32 rd_pos = (fifo_sts >> SPRD_OUTBOX_FIFO_RD_SHIFT) &
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SPRD_OUTBOX_FIFO_POS_MASK;
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u32 fifo_len;
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/*
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* If the read pointer is equal with write pointer, which means the fifo
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* is full or empty.
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*/
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if (wr_pos == rd_pos) {
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if (fifo_sts & SPRD_OUTBOX_FIFO_FULL)
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fifo_len = priv->outbox_fifo_depth;
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else
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fifo_len = 0;
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} else if (wr_pos > rd_pos) {
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fifo_len = wr_pos - rd_pos;
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} else {
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fifo_len = priv->outbox_fifo_depth - rd_pos + wr_pos;
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}
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return fifo_len;
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}
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static irqreturn_t do_outbox_isr(void __iomem *base, struct sprd_mbox_priv *priv)
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{
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struct mbox_chan *chan;
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u32 fifo_sts, fifo_len, msg[2];
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int i, id;
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fifo_sts = readl(base + SPRD_MBOX_FIFO_STS);
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fifo_len = sprd_mbox_get_fifo_len(priv, fifo_sts);
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if (!fifo_len) {
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dev_warn_ratelimited(priv->dev, "spurious outbox interrupt\n");
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return IRQ_NONE;
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}
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for (i = 0; i < fifo_len; i++) {
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msg[0] = readl(base + SPRD_MBOX_MSG_LOW);
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msg[1] = readl(base + SPRD_MBOX_MSG_HIGH);
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id = readl(base + SPRD_MBOX_ID);
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chan = &priv->chan[id];
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if (chan->cl)
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mbox_chan_received_data(chan, (void *)msg);
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else
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dev_warn_ratelimited(priv->dev,
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"message's been dropped at ch[%d]\n", id);
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/* Trigger to update outbox FIFO pointer */
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writel(0x1, base + SPRD_MBOX_TRIGGER);
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}
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/* Clear irq status after reading all message. */
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writel(SPRD_MBOX_IRQ_CLR, base + SPRD_MBOX_IRQ_STS);
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return IRQ_HANDLED;
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}
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static irqreturn_t sprd_mbox_outbox_isr(int irq, void *data)
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{
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struct sprd_mbox_priv *priv = data;
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return do_outbox_isr(priv->outbox_base, priv);
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}
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static irqreturn_t sprd_mbox_supp_isr(int irq, void *data)
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{
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struct sprd_mbox_priv *priv = data;
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return do_outbox_isr(priv->supp_base, priv);
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}
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static irqreturn_t sprd_mbox_inbox_isr(int irq, void *data)
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{
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struct sprd_mbox_priv *priv = data;
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struct mbox_chan *chan;
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u32 fifo_sts, send_sts, busy, id;
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fifo_sts = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS);
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/* Get the inbox data delivery status */
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send_sts = (fifo_sts & SPRD_INBOX_FIFO_DELIVER_MASK) >>
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SPRD_INBOX_FIFO_DELIVER_SHIFT;
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if (!send_sts) {
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dev_warn_ratelimited(priv->dev, "spurious inbox interrupt\n");
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return IRQ_NONE;
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}
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while (send_sts) {
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id = __ffs(send_sts);
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send_sts &= (send_sts - 1);
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chan = &priv->chan[id];
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/*
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* Check if the message was fetched by remote target, if yes,
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* that means the transmission has been completed.
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*/
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busy = fifo_sts & SPRD_INBOX_FIFO_BUSY_MASK;
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if (!(busy & BIT(id)))
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mbox_chan_txdone(chan, 0);
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}
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/* Clear FIFO delivery and overflow status */
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writel(fifo_sts &
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(SPRD_INBOX_FIFO_DELIVER_MASK | SPRD_INBOX_FIFO_OVERLOW_MASK),
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priv->inbox_base + SPRD_MBOX_FIFO_RST);
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/* Clear irq status */
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writel(SPRD_MBOX_IRQ_CLR, priv->inbox_base + SPRD_MBOX_IRQ_STS);
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return IRQ_HANDLED;
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}
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static int sprd_mbox_send_data(struct mbox_chan *chan, void *msg)
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{
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struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
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unsigned long id = (unsigned long)chan->con_priv;
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u32 *data = msg;
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/* Write data into inbox FIFO, and only support 8 bytes every time */
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writel(data[0], priv->inbox_base + SPRD_MBOX_MSG_LOW);
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writel(data[1], priv->inbox_base + SPRD_MBOX_MSG_HIGH);
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/* Set target core id */
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writel(id, priv->inbox_base + SPRD_MBOX_ID);
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/* Trigger remote request */
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writel(0x1, priv->inbox_base + SPRD_MBOX_TRIGGER);
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return 0;
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}
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static int sprd_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
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{
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struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
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unsigned long id = (unsigned long)chan->con_priv;
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u32 busy;
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timeout = jiffies + msecs_to_jiffies(timeout);
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while (time_before(jiffies, timeout)) {
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busy = readl(priv->inbox_base + SPRD_MBOX_FIFO_STS) &
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SPRD_INBOX_FIFO_BUSY_MASK;
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if (!(busy & BIT(id))) {
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mbox_chan_txdone(chan, 0);
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return 0;
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}
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udelay(1);
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}
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return -ETIME;
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}
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static int sprd_mbox_startup(struct mbox_chan *chan)
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{
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struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
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u32 val;
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mutex_lock(&priv->lock);
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if (priv->refcnt++ == 0) {
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/* Select outbox FIFO mode and reset the outbox FIFO status */
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writel(0x0, priv->outbox_base + SPRD_MBOX_FIFO_RST);
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/* Enable inbox FIFO overflow and delivery interrupt */
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val = readl(priv->inbox_base + SPRD_MBOX_IRQ_MSK);
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val &= ~(SPRD_INBOX_FIFO_OVERFLOW_IRQ | SPRD_INBOX_FIFO_DELIVER_IRQ);
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writel(val, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
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/* Enable outbox FIFO not empty interrupt */
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val = readl(priv->outbox_base + SPRD_MBOX_IRQ_MSK);
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val &= ~SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ;
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writel(val, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
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/* Enable supplementary outbox as the fundamental one */
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if (priv->supp_base) {
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writel(0x0, priv->supp_base + SPRD_MBOX_FIFO_RST);
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val = readl(priv->supp_base + SPRD_MBOX_IRQ_MSK);
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val &= ~SPRD_OUTBOX_FIFO_NOT_EMPTY_IRQ;
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writel(val, priv->supp_base + SPRD_MBOX_IRQ_MSK);
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}
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}
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mutex_unlock(&priv->lock);
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return 0;
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}
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static void sprd_mbox_shutdown(struct mbox_chan *chan)
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{
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struct sprd_mbox_priv *priv = to_sprd_mbox_priv(chan->mbox);
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mutex_lock(&priv->lock);
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if (--priv->refcnt == 0) {
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/* Disable inbox & outbox interrupt */
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writel(SPRD_INBOX_FIFO_IRQ_MASK, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
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writel(SPRD_OUTBOX_FIFO_IRQ_MASK, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
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if (priv->supp_base)
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writel(SPRD_OUTBOX_FIFO_IRQ_MASK,
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priv->supp_base + SPRD_MBOX_IRQ_MSK);
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}
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mutex_unlock(&priv->lock);
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}
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static const struct mbox_chan_ops sprd_mbox_ops = {
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.send_data = sprd_mbox_send_data,
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.flush = sprd_mbox_flush,
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.startup = sprd_mbox_startup,
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.shutdown = sprd_mbox_shutdown,
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};
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static void sprd_mbox_disable(void *data)
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{
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struct sprd_mbox_priv *priv = data;
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clk_disable_unprepare(priv->clk);
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}
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static int sprd_mbox_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct sprd_mbox_priv *priv;
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int ret, inbox_irq, outbox_irq, supp_irq;
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unsigned long id, supp;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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mutex_init(&priv->lock);
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/*
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* Unisoc mailbox uses an inbox to send messages to the target
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* core, and uses (an) outbox(es) to receive messages from other
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* cores.
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*
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* Thus in general the mailbox controller supplies 2 different
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* register addresses and IRQ numbers for inbox and outbox.
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*
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* If necessary, a supplementary inbox could be enabled optionally
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* with an independent FIFO and an extra interrupt.
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*/
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priv->inbox_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->inbox_base))
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return PTR_ERR(priv->inbox_base);
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priv->outbox_base = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(priv->outbox_base))
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return PTR_ERR(priv->outbox_base);
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priv->clk = devm_clk_get(dev, "enable");
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if (IS_ERR(priv->clk)) {
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dev_err(dev, "failed to get mailbox clock\n");
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return PTR_ERR(priv->clk);
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}
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, sprd_mbox_disable, priv);
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if (ret) {
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dev_err(dev, "failed to add mailbox disable action\n");
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return ret;
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}
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inbox_irq = platform_get_irq_byname(pdev, "inbox");
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if (inbox_irq < 0)
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return inbox_irq;
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ret = devm_request_irq(dev, inbox_irq, sprd_mbox_inbox_isr,
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IRQF_NO_SUSPEND, dev_name(dev), priv);
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if (ret) {
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dev_err(dev, "failed to request inbox IRQ: %d\n", ret);
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return ret;
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}
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outbox_irq = platform_get_irq_byname(pdev, "outbox");
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if (outbox_irq < 0)
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return outbox_irq;
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ret = devm_request_irq(dev, outbox_irq, sprd_mbox_outbox_isr,
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IRQF_NO_SUSPEND, dev_name(dev), priv);
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if (ret) {
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dev_err(dev, "failed to request outbox IRQ: %d\n", ret);
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return ret;
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}
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/* Supplementary outbox IRQ is optional */
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supp_irq = platform_get_irq_byname(pdev, "supp-outbox");
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if (supp_irq > 0) {
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ret = devm_request_irq(dev, supp_irq, sprd_mbox_supp_isr,
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IRQF_NO_SUSPEND, dev_name(dev), priv);
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if (ret) {
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dev_err(dev, "failed to request outbox IRQ: %d\n", ret);
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return ret;
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}
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supp = (unsigned long) of_device_get_match_data(dev);
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if (!supp) {
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dev_err(dev, "no supplementary outbox specified\n");
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return -ENODEV;
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}
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priv->supp_base = priv->outbox_base + (SPRD_OUTBOX_BASE_SPAN * supp);
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}
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/* Get the default outbox FIFO depth */
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priv->outbox_fifo_depth =
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readl(priv->outbox_base + SPRD_MBOX_FIFO_DEPTH) + 1;
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priv->mbox.dev = dev;
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priv->mbox.chans = &priv->chan[0];
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priv->mbox.num_chans = SPRD_MBOX_CHAN_MAX;
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priv->mbox.ops = &sprd_mbox_ops;
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priv->mbox.txdone_irq = true;
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for (id = 0; id < SPRD_MBOX_CHAN_MAX; id++)
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priv->chan[id].con_priv = (void *)id;
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ret = devm_mbox_controller_register(dev, &priv->mbox);
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if (ret) {
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dev_err(dev, "failed to register mailbox: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct of_device_id sprd_mbox_of_match[] = {
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{ .compatible = "sprd,sc9860-mailbox" },
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{ .compatible = "sprd,sc9863a-mailbox",
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.data = (void *)SPRD_SUPP_INBOX_ID_SC9863A },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sprd_mbox_of_match);
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static struct platform_driver sprd_mbox_driver = {
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.driver = {
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.name = "sprd-mailbox",
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.of_match_table = sprd_mbox_of_match,
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},
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.probe = sprd_mbox_probe,
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};
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module_platform_driver(sprd_mbox_driver);
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MODULE_AUTHOR("Baolin Wang <baolin.wang@unisoc.com>");
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MODULE_DESCRIPTION("Spreadtrum mailbox driver");
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MODULE_LICENSE("GPL v2");
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