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a3d66a7634
Register ARMADA_370_XP_INT_FABRIC_MASK_OFFS is Armada 370 and XP specific
and on new Armada platforms it has different meaning. It does not configure
Performance Counter Overflow interrupt masking. So do not touch this
register on non-A370/XP platforms (A375, A38x and A39x).
Signed-off-by: Pali Rohár <pali@kernel.org>
Cc: stable@vger.kernel.org
Fixes: 28da06dfd9
("irqchip: armada-370-xp: Enable the PMU interrupts")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425113706.29310-1-pali@kernel.org
827 lines
22 KiB
C
827 lines
22 KiB
C
/*
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* Marvell Armada 370 and Armada XP SoC IRQ handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/cpu.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/irqdomain.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/msi.h>
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/irq.h>
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/*
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* Overall diagram of the Armada XP interrupt controller:
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*
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* To CPU 0 To CPU 1
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*
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* /\ /\
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* || ||
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* +---------------+ +---------------+
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* | | | |
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* | per-CPU | | per-CPU |
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* | mask/unmask | | mask/unmask |
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* | CPU0 | | CPU1 |
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* | | | |
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* +---------------+ +---------------+
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* /\ /\
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* || ||
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* \\_______________________//
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* ||
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* +-------------------+
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* | |
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* | Global interrupt |
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* | mask/unmask |
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* | |
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* +-------------------+
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* /\
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* ||
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* interrupt from
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* device
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*
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* The "global interrupt mask/unmask" is modified using the
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* ARMADA_370_XP_INT_SET_ENABLE_OFFS and
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* ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
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* to "main_int_base".
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*
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* The "per-CPU mask/unmask" is modified using the
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* ARMADA_370_XP_INT_SET_MASK_OFFS and
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* ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
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* "per_cpu_int_base". This base address points to a special address,
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* which automatically accesses the registers of the current CPU.
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*
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* The per-CPU mask/unmask can also be adjusted using the global
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* per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
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* to configure interrupt affinity.
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*
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* Due to this model, all interrupts need to be mask/unmasked at two
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* different levels: at the global level and at the per-CPU level.
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*
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* This driver takes the following approach to deal with this:
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*
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* - For global interrupts:
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*
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* At ->map() time, a global interrupt is unmasked at the per-CPU
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* mask/unmask level. It is therefore unmasked at this level for
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* the current CPU, running the ->map() code. This allows to have
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* the interrupt unmasked at this level in non-SMP
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* configurations. In SMP configurations, the ->set_affinity()
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* callback is called, which using the
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* ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
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* for the interrupt.
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*
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* The ->mask() and ->unmask() operations only mask/unmask the
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* interrupt at the "global" level.
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*
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* So, a global interrupt is enabled at the per-CPU level as soon
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* as it is mapped. At run time, the masking/unmasking takes place
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* at the global level.
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*
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* - For per-CPU interrupts
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*
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* At ->map() time, a per-CPU interrupt is unmasked at the global
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* mask/unmask level.
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*
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* The ->mask() and ->unmask() operations mask/unmask the interrupt
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* at the per-CPU level.
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*
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* So, a per-CPU interrupt is enabled at the global level as soon
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* as it is mapped. At run time, the masking/unmasking takes place
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* at the per-CPU level.
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*/
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/* Registers relative to main_int_base */
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#define ARMADA_370_XP_INT_CONTROL (0x00)
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#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04)
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
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#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
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#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
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#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
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/* Registers relative to per_cpu_int_base */
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#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08)
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#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c)
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#define ARMADA_375_PPI_CAUSE (0x10)
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
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#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
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#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
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#define IPI_DOORBELL_START (0)
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#define IPI_DOORBELL_END (8)
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#define IPI_DOORBELL_MASK 0xFF
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#define PCI_MSI_DOORBELL_START (16)
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#define PCI_MSI_DOORBELL_NR (16)
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#define PCI_MSI_DOORBELL_END (32)
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#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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static u32 doorbell_mask_reg;
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static int parent_irq;
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#ifdef CONFIG_PCI_MSI
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static struct irq_domain *armada_370_xp_msi_domain;
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static struct irq_domain *armada_370_xp_msi_inner_domain;
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static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
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static DEFINE_MUTEX(msi_used_lock);
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static phys_addr_t msi_doorbell_addr;
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#endif
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static inline bool is_percpu_irq(irq_hw_number_t irq)
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{
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if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
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return true;
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return false;
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}
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/*
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* In SMP mode:
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* For shared global interrupts, mask/unmask global enable bit
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* For CPU interrupts, mask/unmask the calling CPU's bit
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*/
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static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (!is_percpu_irq(hwirq))
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_SET_MASK_OFFS);
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}
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static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (!is_percpu_irq(hwirq))
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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#ifdef CONFIG_PCI_MSI
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static struct irq_chip armada_370_xp_msi_irq_chip = {
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.name = "MPIC MSI",
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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static struct msi_domain_info armada_370_xp_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
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.chip = &armada_370_xp_msi_irq_chip,
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};
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static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(data));
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msg->address_lo = lower_32_bits(msi_doorbell_addr);
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msg->address_hi = upper_32_bits(msi_doorbell_addr);
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msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START);
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}
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static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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unsigned int cpu;
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if (!force)
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cpu = cpumask_any_and(mask, cpu_online_mask);
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else
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cpu = cpumask_first(mask);
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if (cpu >= nr_cpu_ids)
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return -EINVAL;
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irq_data_update_effective_affinity(irq_data, cpumask_of(cpu));
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return IRQ_SET_MASK_OK;
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}
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static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
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.name = "MPIC MSI",
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.irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
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.irq_set_affinity = armada_370_xp_msi_set_affinity,
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};
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static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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int hwirq, i;
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mutex_lock(&msi_used_lock);
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hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR,
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order_base_2(nr_irqs));
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mutex_unlock(&msi_used_lock);
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if (hwirq < 0)
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return -ENOSPC;
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for (i = 0; i < nr_irqs; i++) {
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irq_domain_set_info(domain, virq + i, hwirq + i,
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&armada_370_xp_msi_bottom_irq_chip,
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domain->host_data, handle_simple_irq,
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NULL, NULL);
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}
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return 0;
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}
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static void armada_370_xp_msi_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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mutex_lock(&msi_used_lock);
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bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));
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mutex_unlock(&msi_used_lock);
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}
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static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
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.alloc = armada_370_xp_msi_alloc,
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.free = armada_370_xp_msi_free,
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};
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static void armada_370_xp_msi_reenable_percpu(void)
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{
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u32 reg;
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/* Enable MSI doorbell mask and combined cpu local interrupt */
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reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
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| PCI_MSI_DOORBELL_MASK;
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writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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/* Unmask local doorbell interrupt */
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writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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static int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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{
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msi_doorbell_addr = main_int_phys_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS;
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armada_370_xp_msi_inner_domain =
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irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
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&armada_370_xp_msi_domain_ops, NULL);
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if (!armada_370_xp_msi_inner_domain)
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return -ENOMEM;
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armada_370_xp_msi_domain =
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pci_msi_create_irq_domain(of_node_to_fwnode(node),
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&armada_370_xp_msi_domain_info,
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armada_370_xp_msi_inner_domain);
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if (!armada_370_xp_msi_domain) {
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irq_domain_remove(armada_370_xp_msi_inner_domain);
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return -ENOMEM;
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}
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armada_370_xp_msi_reenable_percpu();
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return 0;
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}
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#else
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static void armada_370_xp_msi_reenable_percpu(void) {}
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static inline int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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{
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return 0;
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}
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#endif
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static void armada_xp_mpic_perf_init(void)
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{
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unsigned long cpuid;
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/*
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* This Performance Counter Overflow interrupt is specific for
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* Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
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*/
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if (!of_machine_is_compatible("marvell,armada-370-xp"))
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return;
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cpuid = cpu_logical_map(smp_processor_id());
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/* Enable Performance Counter Overflow interrupts */
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writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
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per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
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}
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#ifdef CONFIG_SMP
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static struct irq_domain *ipi_domain;
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static void armada_370_xp_ipi_mask(struct irq_data *d)
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{
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u32 reg;
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reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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reg &= ~BIT(d->hwirq);
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writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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}
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static void armada_370_xp_ipi_unmask(struct irq_data *d)
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{
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u32 reg;
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reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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reg |= BIT(d->hwirq);
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writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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}
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static void armada_370_xp_ipi_send_mask(struct irq_data *d,
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const struct cpumask *mask)
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{
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unsigned long map = 0;
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int cpu;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= 1 << cpu_logical_map(cpu);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* submit softirq */
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writel((map << 8) | d->hwirq, main_int_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS);
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}
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static void armada_370_xp_ipi_ack(struct irq_data *d)
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{
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writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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}
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static struct irq_chip ipi_irqchip = {
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.name = "IPI",
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.irq_ack = armada_370_xp_ipi_ack,
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.irq_mask = armada_370_xp_ipi_mask,
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.irq_unmask = armada_370_xp_ipi_unmask,
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.ipi_send_mask = armada_370_xp_ipi_send_mask,
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};
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static int armada_370_xp_ipi_alloc(struct irq_domain *d,
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unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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int i;
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for (i = 0; i < nr_irqs; i++) {
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irq_set_percpu_devid(virq + i);
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irq_domain_set_info(d, virq + i, i, &ipi_irqchip,
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d->host_data,
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handle_percpu_devid_irq,
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NULL, NULL);
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}
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return 0;
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}
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static void armada_370_xp_ipi_free(struct irq_domain *d,
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unsigned int virq,
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unsigned int nr_irqs)
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{
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/* Not freeing IPIs */
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}
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static const struct irq_domain_ops ipi_domain_ops = {
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.alloc = armada_370_xp_ipi_alloc,
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.free = armada_370_xp_ipi_free,
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};
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static void ipi_resume(void)
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{
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int i;
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for (i = 0; i < IPI_DOORBELL_END; i++) {
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int irq;
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irq = irq_find_mapping(ipi_domain, i);
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if (irq <= 0)
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continue;
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if (irq_percpu_is_enabled(irq)) {
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struct irq_data *d;
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d = irq_domain_get_irq_data(ipi_domain, irq);
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armada_370_xp_ipi_unmask(d);
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}
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}
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}
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static __init void armada_xp_ipi_init(struct device_node *node)
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{
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int base_ipi;
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ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node),
|
|
IPI_DOORBELL_END,
|
|
&ipi_domain_ops, NULL);
|
|
if (WARN_ON(!ipi_domain))
|
|
return;
|
|
|
|
irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
|
|
base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, IPI_DOORBELL_END,
|
|
NUMA_NO_NODE, NULL, false, NULL);
|
|
if (WARN_ON(!base_ipi))
|
|
return;
|
|
|
|
set_smp_ipi_range(base_ipi, IPI_DOORBELL_END);
|
|
}
|
|
|
|
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
|
|
|
|
static int armada_xp_set_affinity(struct irq_data *d,
|
|
const struct cpumask *mask_val, bool force)
|
|
{
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
|
unsigned long reg, mask;
|
|
int cpu;
|
|
|
|
/* Select a single core from the affinity mask which is online */
|
|
cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
|
mask = 1UL << cpu_logical_map(cpu);
|
|
|
|
raw_spin_lock(&irq_controller_lock);
|
|
reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
|
|
reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
|
|
writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
|
|
raw_spin_unlock(&irq_controller_lock);
|
|
|
|
irq_data_update_effective_affinity(d, cpumask_of(cpu));
|
|
|
|
return IRQ_SET_MASK_OK;
|
|
}
|
|
|
|
static void armada_xp_mpic_smp_cpu_init(void)
|
|
{
|
|
u32 control;
|
|
int nr_irqs, i;
|
|
|
|
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
|
|
nr_irqs = (control >> 2) & 0x3ff;
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
|
|
|
|
/* Disable all IPIs */
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
|
|
/* Clear pending IPIs */
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
/* Unmask IPI interrupt */
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
}
|
|
|
|
static void armada_xp_mpic_reenable_percpu(void)
|
|
{
|
|
unsigned int irq;
|
|
|
|
/* Re-enable per-CPU interrupts that were enabled before suspend */
|
|
for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
|
|
struct irq_data *data;
|
|
int virq;
|
|
|
|
virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
|
|
if (virq == 0)
|
|
continue;
|
|
|
|
data = irq_get_irq_data(virq);
|
|
|
|
if (!irq_percpu_is_enabled(virq))
|
|
continue;
|
|
|
|
armada_370_xp_irq_unmask(data);
|
|
}
|
|
|
|
ipi_resume();
|
|
|
|
armada_370_xp_msi_reenable_percpu();
|
|
}
|
|
|
|
static int armada_xp_mpic_starting_cpu(unsigned int cpu)
|
|
{
|
|
armada_xp_mpic_perf_init();
|
|
armada_xp_mpic_smp_cpu_init();
|
|
armada_xp_mpic_reenable_percpu();
|
|
return 0;
|
|
}
|
|
|
|
static int mpic_cascaded_starting_cpu(unsigned int cpu)
|
|
{
|
|
armada_xp_mpic_perf_init();
|
|
armada_xp_mpic_reenable_percpu();
|
|
enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
|
|
return 0;
|
|
}
|
|
#else
|
|
static void armada_xp_mpic_smp_cpu_init(void) {}
|
|
static void ipi_resume(void) {}
|
|
#endif
|
|
|
|
static struct irq_chip armada_370_xp_irq_chip = {
|
|
.name = "MPIC",
|
|
.irq_mask = armada_370_xp_irq_mask,
|
|
.irq_mask_ack = armada_370_xp_irq_mask,
|
|
.irq_unmask = armada_370_xp_irq_unmask,
|
|
#ifdef CONFIG_SMP
|
|
.irq_set_affinity = armada_xp_set_affinity,
|
|
#endif
|
|
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
|
|
};
|
|
|
|
static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
|
|
unsigned int virq, irq_hw_number_t hw)
|
|
{
|
|
armada_370_xp_irq_mask(irq_get_irq_data(virq));
|
|
if (!is_percpu_irq(hw))
|
|
writel(hw, per_cpu_int_base +
|
|
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
else
|
|
writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
|
irq_set_status_flags(virq, IRQ_LEVEL);
|
|
|
|
if (is_percpu_irq(hw)) {
|
|
irq_set_percpu_devid(virq);
|
|
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
|
|
handle_percpu_devid_irq);
|
|
} else {
|
|
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
|
|
handle_level_irq);
|
|
irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
|
|
}
|
|
irq_set_probe(virq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
|
|
.map = armada_370_xp_mpic_irq_map,
|
|
.xlate = irq_domain_xlate_onecell,
|
|
};
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
|
|
{
|
|
u32 msimask, msinr;
|
|
|
|
msimask = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
|
|
& PCI_MSI_DOORBELL_MASK;
|
|
|
|
writel(~msimask, per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
for (msinr = PCI_MSI_DOORBELL_START;
|
|
msinr < PCI_MSI_DOORBELL_END; msinr++) {
|
|
unsigned int irq;
|
|
|
|
if (!(msimask & BIT(msinr)))
|
|
continue;
|
|
|
|
irq = msinr - PCI_MSI_DOORBELL_START;
|
|
|
|
generic_handle_domain_irq(armada_370_xp_msi_inner_domain, irq);
|
|
}
|
|
}
|
|
#else
|
|
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
|
|
#endif
|
|
|
|
static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
unsigned long irqmap, irqn, irqsrc, cpuid;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
|
|
irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
|
|
cpuid = cpu_logical_map(smp_processor_id());
|
|
|
|
for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
|
|
irqsrc = readl_relaxed(main_int_base +
|
|
ARMADA_370_XP_INT_SOURCE_CTL(irqn));
|
|
|
|
/* Check if the interrupt is not masked on current CPU.
|
|
* Test IRQ (0-1) and FIQ (8-9) mask bits.
|
|
*/
|
|
if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
|
|
continue;
|
|
|
|
if (irqn == 1) {
|
|
armada_370_xp_handle_msi_irq(NULL, true);
|
|
continue;
|
|
}
|
|
|
|
generic_handle_domain_irq(armada_370_xp_mpic_domain, irqn);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static void __exception_irq_entry
|
|
armada_370_xp_handle_irq(struct pt_regs *regs)
|
|
{
|
|
u32 irqstat, irqnr;
|
|
|
|
do {
|
|
irqstat = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_CPU_INTACK_OFFS);
|
|
irqnr = irqstat & 0x3FF;
|
|
|
|
if (irqnr > 1022)
|
|
break;
|
|
|
|
if (irqnr > 1) {
|
|
generic_handle_domain_irq(armada_370_xp_mpic_domain,
|
|
irqnr);
|
|
continue;
|
|
}
|
|
|
|
/* MSI handling */
|
|
if (irqnr == 1)
|
|
armada_370_xp_handle_msi_irq(regs, false);
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* IPI Handling */
|
|
if (irqnr == 0) {
|
|
unsigned long ipimask;
|
|
int ipi;
|
|
|
|
ipimask = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
|
|
& IPI_DOORBELL_MASK;
|
|
|
|
for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END)
|
|
generic_handle_domain_irq(ipi_domain, ipi);
|
|
}
|
|
#endif
|
|
|
|
} while (1);
|
|
}
|
|
|
|
static int armada_370_xp_mpic_suspend(void)
|
|
{
|
|
doorbell_mask_reg = readl(per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
return 0;
|
|
}
|
|
|
|
static void armada_370_xp_mpic_resume(void)
|
|
{
|
|
int nirqs;
|
|
irq_hw_number_t irq;
|
|
|
|
/* Re-enable interrupts */
|
|
nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
|
|
for (irq = 0; irq < nirqs; irq++) {
|
|
struct irq_data *data;
|
|
int virq;
|
|
|
|
virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
|
|
if (virq == 0)
|
|
continue;
|
|
|
|
data = irq_get_irq_data(virq);
|
|
|
|
if (!is_percpu_irq(irq)) {
|
|
/* Non per-CPU interrupts */
|
|
writel(irq, per_cpu_int_base +
|
|
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
if (!irqd_irq_disabled(data))
|
|
armada_370_xp_irq_unmask(data);
|
|
} else {
|
|
/* Per-CPU interrupts */
|
|
writel(irq, main_int_base +
|
|
ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
|
|
|
/*
|
|
* Re-enable on the current CPU,
|
|
* armada_xp_mpic_reenable_percpu() will take
|
|
* care of secondary CPUs when they come up.
|
|
*/
|
|
if (irq_percpu_is_enabled(virq))
|
|
armada_370_xp_irq_unmask(data);
|
|
}
|
|
}
|
|
|
|
/* Reconfigure doorbells for IPIs and MSIs */
|
|
writel(doorbell_mask_reg,
|
|
per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
if (doorbell_mask_reg & IPI_DOORBELL_MASK)
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
|
|
writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
|
|
ipi_resume();
|
|
}
|
|
|
|
static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
|
|
.suspend = armada_370_xp_mpic_suspend,
|
|
.resume = armada_370_xp_mpic_resume,
|
|
};
|
|
|
|
static int __init armada_370_xp_mpic_of_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
struct resource main_int_res, per_cpu_int_res;
|
|
int nr_irqs, i;
|
|
u32 control;
|
|
|
|
BUG_ON(of_address_to_resource(node, 0, &main_int_res));
|
|
BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
|
|
|
|
BUG_ON(!request_mem_region(main_int_res.start,
|
|
resource_size(&main_int_res),
|
|
node->full_name));
|
|
BUG_ON(!request_mem_region(per_cpu_int_res.start,
|
|
resource_size(&per_cpu_int_res),
|
|
node->full_name));
|
|
|
|
main_int_base = ioremap(main_int_res.start,
|
|
resource_size(&main_int_res));
|
|
BUG_ON(!main_int_base);
|
|
|
|
per_cpu_int_base = ioremap(per_cpu_int_res.start,
|
|
resource_size(&per_cpu_int_res));
|
|
BUG_ON(!per_cpu_int_base);
|
|
|
|
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
|
|
nr_irqs = (control >> 2) & 0x3ff;
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
|
|
|
|
armada_370_xp_mpic_domain =
|
|
irq_domain_add_linear(node, nr_irqs,
|
|
&armada_370_xp_mpic_irq_ops, NULL);
|
|
BUG_ON(!armada_370_xp_mpic_domain);
|
|
irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
|
|
|
|
/* Setup for the boot CPU */
|
|
armada_xp_mpic_perf_init();
|
|
armada_xp_mpic_smp_cpu_init();
|
|
|
|
armada_370_xp_msi_init(node, main_int_res.start);
|
|
|
|
parent_irq = irq_of_parse_and_map(node, 0);
|
|
if (parent_irq <= 0) {
|
|
irq_set_default_host(armada_370_xp_mpic_domain);
|
|
set_handle_irq(armada_370_xp_handle_irq);
|
|
#ifdef CONFIG_SMP
|
|
armada_xp_ipi_init(node);
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
|
|
"irqchip/armada/ipi:starting",
|
|
armada_xp_mpic_starting_cpu, NULL);
|
|
#endif
|
|
} else {
|
|
#ifdef CONFIG_SMP
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
|
|
"irqchip/armada/cascade:starting",
|
|
mpic_cascaded_starting_cpu, NULL);
|
|
#endif
|
|
irq_set_chained_handler(parent_irq,
|
|
armada_370_xp_mpic_handle_cascade_irq);
|
|
}
|
|
|
|
register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
|