mirror of
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e75d678d04
This fixes device lifetime issues where it was possible to free a live
struct device.
Fixes: 597f55e3f3
("counter: stm32-lptimer: add counter device")
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20211230150300.72196-22-u.kleine-koenig@pengutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
523 lines
13 KiB
C
523 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* STM32 Low-Power Timer Encoder and Counter driver
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*
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* Copyright (C) STMicroelectronics 2017
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*
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
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*
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* Inspired by 104-quad-8 and stm32-timer-trigger drivers.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/counter.h>
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#include <linux/mfd/stm32-lptimer.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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struct stm32_lptim_cnt {
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struct device *dev;
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struct regmap *regmap;
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struct clk *clk;
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u32 ceiling;
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u32 polarity;
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u32 quadrature_mode;
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bool enabled;
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};
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static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
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{
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u32 val;
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int ret;
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ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
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if (ret)
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return ret;
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return FIELD_GET(STM32_LPTIM_ENABLE, val);
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}
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static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
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int enable)
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{
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int ret;
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u32 val;
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val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
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ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
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if (ret)
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return ret;
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if (!enable) {
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clk_disable(priv->clk);
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priv->enabled = false;
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return 0;
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}
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/* LP timer must be enabled before writing CMP & ARR */
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ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
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if (ret)
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return ret;
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ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
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if (ret)
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return ret;
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/* ensure CMP & ARR registers are properly written */
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ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
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(val & STM32_LPTIM_CMPOK_ARROK),
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100, 1000);
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if (ret)
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return ret;
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ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
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STM32_LPTIM_CMPOKCF_ARROKCF);
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if (ret)
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return ret;
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ret = clk_enable(priv->clk);
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if (ret) {
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regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
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return ret;
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}
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priv->enabled = true;
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/* Start LP timer in continuous mode */
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return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
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STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
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}
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static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
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{
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u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |
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STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;
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u32 val;
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/* Setup LP timer encoder/counter and polarity, without prescaler */
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if (priv->quadrature_mode)
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val = enable ? STM32_LPTIM_ENC : 0;
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else
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val = enable ? STM32_LPTIM_COUNTMODE : 0;
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val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);
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return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
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}
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/*
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* In non-quadrature mode, device counts up on active edge.
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* In quadrature mode, encoder counting scenarios are as follows:
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* +---------+----------+--------------------+--------------------+
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* | Active | Level on | IN1 signal | IN2 signal |
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* | edge | opposite +----------+---------+----------+---------+
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* | | signal | Rising | Falling | Rising | Falling |
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* +---------+----------+----------+---------+----------+---------+
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* | Rising | High -> | Down | - | Up | - |
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* | edge | Low -> | Up | - | Down | - |
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* +---------+----------+----------+---------+----------+---------+
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* | Falling | High -> | - | Up | - | Down |
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* | edge | Low -> | - | Down | - | Up |
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* +---------+----------+----------+---------+----------+---------+
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* | Both | High -> | Down | Up | Up | Down |
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* | edges | Low -> | Up | Down | Down | Up |
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* +---------+----------+----------+---------+----------+---------+
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*/
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static const enum counter_function stm32_lptim_cnt_functions[] = {
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COUNTER_FUNCTION_INCREASE,
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COUNTER_FUNCTION_QUADRATURE_X4,
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};
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static const enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
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COUNTER_SYNAPSE_ACTION_RISING_EDGE,
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COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
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COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
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COUNTER_SYNAPSE_ACTION_NONE,
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};
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static int stm32_lptim_cnt_read(struct counter_device *counter,
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struct counter_count *count, u64 *val)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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u32 cnt;
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int ret;
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ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
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if (ret)
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return ret;
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*val = cnt;
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return 0;
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}
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static int stm32_lptim_cnt_function_read(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function *function)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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if (!priv->quadrature_mode) {
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*function = COUNTER_FUNCTION_INCREASE;
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return 0;
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}
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if (priv->polarity == STM32_LPTIM_CKPOL_BOTH_EDGES) {
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*function = COUNTER_FUNCTION_QUADRATURE_X4;
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return 0;
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}
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return -EINVAL;
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}
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static int stm32_lptim_cnt_function_write(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function function)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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if (stm32_lptim_is_enabled(priv))
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return -EBUSY;
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switch (function) {
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case COUNTER_FUNCTION_INCREASE:
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priv->quadrature_mode = 0;
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X4:
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priv->quadrature_mode = 1;
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priv->polarity = STM32_LPTIM_CKPOL_BOTH_EDGES;
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return 0;
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default:
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/* should never reach this path */
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return -EINVAL;
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}
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}
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static int stm32_lptim_cnt_enable_read(struct counter_device *counter,
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struct counter_count *count,
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u8 *enable)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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int ret;
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ret = stm32_lptim_is_enabled(priv);
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if (ret < 0)
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return ret;
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*enable = ret;
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return 0;
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}
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static int stm32_lptim_cnt_enable_write(struct counter_device *counter,
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struct counter_count *count,
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u8 enable)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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int ret;
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/* Check nobody uses the timer, or already disabled/enabled */
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ret = stm32_lptim_is_enabled(priv);
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if ((ret < 0) || (!ret && !enable))
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return ret;
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if (enable && ret)
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return -EBUSY;
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ret = stm32_lptim_setup(priv, enable);
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if (ret)
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return ret;
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ret = stm32_lptim_set_enable_state(priv, enable);
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if (ret)
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return ret;
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return 0;
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}
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static int stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
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struct counter_count *count,
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u64 *ceiling)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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*ceiling = priv->ceiling;
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return 0;
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}
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static int stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
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struct counter_count *count,
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u64 ceiling)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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if (stm32_lptim_is_enabled(priv))
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return -EBUSY;
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if (ceiling > STM32_LPTIM_MAX_ARR)
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return -ERANGE;
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priv->ceiling = ceiling;
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return 0;
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}
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static struct counter_comp stm32_lptim_cnt_ext[] = {
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COUNTER_COMP_ENABLE(stm32_lptim_cnt_enable_read,
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stm32_lptim_cnt_enable_write),
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COUNTER_COMP_CEILING(stm32_lptim_cnt_ceiling_read,
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stm32_lptim_cnt_ceiling_write),
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};
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static int stm32_lptim_cnt_action_read(struct counter_device *counter,
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struct counter_count *count,
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struct counter_synapse *synapse,
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enum counter_synapse_action *action)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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enum counter_function function;
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int err;
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err = stm32_lptim_cnt_function_read(counter, count, &function);
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if (err)
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return err;
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switch (function) {
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case COUNTER_FUNCTION_INCREASE:
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/* LP Timer acts as up-counter on input 1 */
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if (synapse->signal->id != count->synapses[0].signal->id) {
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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return 0;
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}
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switch (priv->polarity) {
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case STM32_LPTIM_CKPOL_RISING_EDGE:
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*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
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return 0;
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case STM32_LPTIM_CKPOL_FALLING_EDGE:
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*action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
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return 0;
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case STM32_LPTIM_CKPOL_BOTH_EDGES:
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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return 0;
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default:
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/* should never reach this path */
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return -EINVAL;
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}
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case COUNTER_FUNCTION_QUADRATURE_X4:
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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return 0;
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default:
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/* should never reach this path */
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return -EINVAL;
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}
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}
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static int stm32_lptim_cnt_action_write(struct counter_device *counter,
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struct counter_count *count,
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struct counter_synapse *synapse,
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enum counter_synapse_action action)
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{
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struct stm32_lptim_cnt *const priv = counter_priv(counter);
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enum counter_function function;
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int err;
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if (stm32_lptim_is_enabled(priv))
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return -EBUSY;
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err = stm32_lptim_cnt_function_read(counter, count, &function);
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if (err)
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return err;
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/* only set polarity when in counter mode (on input 1) */
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if (function != COUNTER_FUNCTION_INCREASE
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|| synapse->signal->id != count->synapses[0].signal->id)
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return -EINVAL;
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switch (action) {
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case COUNTER_SYNAPSE_ACTION_RISING_EDGE:
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priv->polarity = STM32_LPTIM_CKPOL_RISING_EDGE;
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return 0;
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case COUNTER_SYNAPSE_ACTION_FALLING_EDGE:
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priv->polarity = STM32_LPTIM_CKPOL_FALLING_EDGE;
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return 0;
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case COUNTER_SYNAPSE_ACTION_BOTH_EDGES:
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priv->polarity = STM32_LPTIM_CKPOL_BOTH_EDGES;
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return 0;
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default:
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return -EINVAL;
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}
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}
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static const struct counter_ops stm32_lptim_cnt_ops = {
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.count_read = stm32_lptim_cnt_read,
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.function_read = stm32_lptim_cnt_function_read,
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.function_write = stm32_lptim_cnt_function_write,
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.action_read = stm32_lptim_cnt_action_read,
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.action_write = stm32_lptim_cnt_action_write,
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};
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static struct counter_signal stm32_lptim_cnt_signals[] = {
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{
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.id = 0,
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.name = "Channel 1 Quadrature A"
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},
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{
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.id = 1,
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.name = "Channel 1 Quadrature B"
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}
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};
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static struct counter_synapse stm32_lptim_cnt_synapses[] = {
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{
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.actions_list = stm32_lptim_cnt_synapse_actions,
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.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
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.signal = &stm32_lptim_cnt_signals[0]
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},
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{
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.actions_list = stm32_lptim_cnt_synapse_actions,
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.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
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.signal = &stm32_lptim_cnt_signals[1]
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}
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};
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/* LP timer with encoder */
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static struct counter_count stm32_lptim_enc_counts = {
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.id = 0,
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.name = "LPTimer Count",
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.functions_list = stm32_lptim_cnt_functions,
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.num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
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.synapses = stm32_lptim_cnt_synapses,
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.num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
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.ext = stm32_lptim_cnt_ext,
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.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
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};
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/* LP timer without encoder (counter only) */
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static struct counter_count stm32_lptim_in1_counts = {
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.id = 0,
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.name = "LPTimer Count",
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.functions_list = stm32_lptim_cnt_functions,
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.num_functions = 1,
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.synapses = stm32_lptim_cnt_synapses,
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.num_synapses = 1,
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.ext = stm32_lptim_cnt_ext,
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.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
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};
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static int stm32_lptim_cnt_probe(struct platform_device *pdev)
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{
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struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
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struct counter_device *counter;
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struct stm32_lptim_cnt *priv;
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int ret;
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if (IS_ERR_OR_NULL(ddata))
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return -EINVAL;
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counter = devm_counter_alloc(&pdev->dev, sizeof(*priv));
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if (!counter)
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return -ENOMEM;
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priv = counter_priv(counter);
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priv->dev = &pdev->dev;
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priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
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priv->ceiling = STM32_LPTIM_MAX_ARR;
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/* Initialize Counter device */
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counter->name = dev_name(&pdev->dev);
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counter->parent = &pdev->dev;
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counter->ops = &stm32_lptim_cnt_ops;
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if (ddata->has_encoder) {
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counter->counts = &stm32_lptim_enc_counts;
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counter->num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
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} else {
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counter->counts = &stm32_lptim_in1_counts;
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counter->num_signals = 1;
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}
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counter->num_counts = 1;
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counter->signals = stm32_lptim_cnt_signals;
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platform_set_drvdata(pdev, priv);
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ret = devm_counter_add(&pdev->dev, counter);
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if (ret < 0)
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return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n");
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int stm32_lptim_cnt_suspend(struct device *dev)
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{
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struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
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int ret;
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/* Only take care of enabled counter: don't disturb other MFD child */
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if (priv->enabled) {
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ret = stm32_lptim_setup(priv, 0);
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if (ret)
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return ret;
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ret = stm32_lptim_set_enable_state(priv, 0);
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if (ret)
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return ret;
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/* Force enable state for later resume */
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priv->enabled = true;
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}
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return pinctrl_pm_select_sleep_state(dev);
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}
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static int stm32_lptim_cnt_resume(struct device *dev)
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{
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struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
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int ret;
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ret = pinctrl_pm_select_default_state(dev);
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if (ret)
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return ret;
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if (priv->enabled) {
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priv->enabled = false;
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ret = stm32_lptim_setup(priv, 1);
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if (ret)
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return ret;
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ret = stm32_lptim_set_enable_state(priv, 1);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
|
|
stm32_lptim_cnt_resume);
|
|
|
|
static const struct of_device_id stm32_lptim_cnt_of_match[] = {
|
|
{ .compatible = "st,stm32-lptimer-counter", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);
|
|
|
|
static struct platform_driver stm32_lptim_cnt_driver = {
|
|
.probe = stm32_lptim_cnt_probe,
|
|
.driver = {
|
|
.name = "stm32-lptimer-counter",
|
|
.of_match_table = stm32_lptim_cnt_of_match,
|
|
.pm = &stm32_lptim_cnt_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(stm32_lptim_cnt_driver);
|
|
|
|
MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
|
|
MODULE_ALIAS("platform:stm32-lptimer-counter");
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
|
|
MODULE_LICENSE("GPL v2");
|