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663d8fb0f8
On unbind an irq might be pending which results in quad8_irq_handler()
calling counter_push_event() for a counter that is already unregistered.
This patch fixes that situation by passing the struct counter_device dev
to devm_request_irq() rather than the parent's so that the irq handler
is cleaned before the counter is unregistered.
Fixes: 7aa2ba0df6
("counter: 104-quad-8: Add IRQ support for the ACCES 104-QUAD-8")
Cc: Syed Nayyar Waris <syednwaris@gmail.com>
Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Link: https://lore.kernel.org/r/20220105093052.258791-1-vilhelm.gray@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1215 lines
34 KiB
C
1215 lines
34 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Counter driver for the ACCES 104-QUAD-8
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* Copyright (C) 2016 William Breathitt Gray
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*
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* This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
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*/
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#include <linux/bitops.h>
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#include <linux/counter.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#define QUAD8_EXTENT 32
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static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
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static unsigned int num_quad8;
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module_param_hw_array(base, uint, ioport, &num_quad8, 0);
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MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
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static unsigned int irq[max_num_isa_dev(QUAD8_EXTENT)];
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module_param_hw_array(irq, uint, irq, NULL, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
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#define QUAD8_NUM_COUNTERS 8
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/**
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* struct quad8 - device private data structure
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* @lock: lock to prevent clobbering device states during R/W ops
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* @counter: instance of the counter_device
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* @fck_prescaler: array of filter clock prescaler configurations
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* @preset: array of preset values
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* @count_mode: array of count mode configurations
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* @quadrature_mode: array of quadrature mode configurations
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* @quadrature_scale: array of quadrature mode scale configurations
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* @ab_enable: array of A and B inputs enable configurations
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* @preset_enable: array of set_to_preset_on_index attribute configurations
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* @irq_trigger: array of current IRQ trigger function configurations
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* @synchronous_mode: array of index function synchronous mode configurations
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* @index_polarity: array of index function polarity configurations
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* @cable_fault_enable: differential encoder cable status enable configurations
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* @base: base port address of the device
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*/
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struct quad8 {
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spinlock_t lock;
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unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
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unsigned int preset[QUAD8_NUM_COUNTERS];
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unsigned int count_mode[QUAD8_NUM_COUNTERS];
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unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
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unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
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unsigned int ab_enable[QUAD8_NUM_COUNTERS];
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unsigned int preset_enable[QUAD8_NUM_COUNTERS];
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unsigned int irq_trigger[QUAD8_NUM_COUNTERS];
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unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
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unsigned int index_polarity[QUAD8_NUM_COUNTERS];
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unsigned int cable_fault_enable;
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unsigned int base;
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};
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#define QUAD8_REG_INTERRUPT_STATUS 0x10
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#define QUAD8_REG_CHAN_OP 0x11
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#define QUAD8_REG_INDEX_INTERRUPT 0x12
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#define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
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#define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17
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/* Borrow Toggle flip-flop */
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#define QUAD8_FLAG_BT BIT(0)
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/* Carry Toggle flip-flop */
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#define QUAD8_FLAG_CT BIT(1)
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/* Error flag */
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#define QUAD8_FLAG_E BIT(4)
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/* Up/Down flag */
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#define QUAD8_FLAG_UD BIT(5)
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/* Reset and Load Signal Decoders */
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#define QUAD8_CTR_RLD 0x00
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/* Counter Mode Register */
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#define QUAD8_CTR_CMR 0x20
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/* Input / Output Control Register */
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#define QUAD8_CTR_IOR 0x40
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/* Index Control Register */
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#define QUAD8_CTR_IDR 0x60
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/* Reset Byte Pointer (three byte data pointer) */
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#define QUAD8_RLD_RESET_BP 0x01
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/* Reset Counter */
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#define QUAD8_RLD_RESET_CNTR 0x02
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/* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
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#define QUAD8_RLD_RESET_FLAGS 0x04
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/* Reset Error flag */
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#define QUAD8_RLD_RESET_E 0x06
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/* Preset Register to Counter */
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#define QUAD8_RLD_PRESET_CNTR 0x08
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/* Transfer Counter to Output Latch */
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#define QUAD8_RLD_CNTR_OUT 0x10
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/* Transfer Preset Register LSB to FCK Prescaler */
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#define QUAD8_RLD_PRESET_PSC 0x18
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#define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
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#define QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC 0x04
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#define QUAD8_CMR_QUADRATURE_X1 0x08
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#define QUAD8_CMR_QUADRATURE_X2 0x10
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#define QUAD8_CMR_QUADRATURE_X4 0x18
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static int quad8_signal_read(struct counter_device *counter,
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struct counter_signal *signal,
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enum counter_signal_level *level)
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{
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const struct quad8 *const priv = counter_priv(counter);
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unsigned int state;
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/* Only Index signal levels can be read */
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if (signal->id < 16)
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return -EINVAL;
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state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
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& BIT(signal->id - 16);
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*level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
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return 0;
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}
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static int quad8_count_read(struct counter_device *counter,
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struct counter_count *count, u64 *val)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int base_offset = priv->base + 2 * count->id;
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unsigned int flags;
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unsigned int borrow;
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unsigned int carry;
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unsigned long irqflags;
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int i;
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flags = inb(base_offset + 1);
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borrow = flags & QUAD8_FLAG_BT;
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carry = !!(flags & QUAD8_FLAG_CT);
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/* Borrow XOR Carry effectively doubles count range */
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*val = (unsigned long)(borrow ^ carry) << 24;
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Reset Byte Pointer; transfer Counter to Output Latch */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
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base_offset + 1);
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for (i = 0; i < 3; i++)
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*val |= (unsigned long)inb(base_offset) << (8 * i);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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static int quad8_count_write(struct counter_device *counter,
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struct counter_count *count, u64 val)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int base_offset = priv->base + 2 * count->id;
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unsigned long irqflags;
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int i;
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/* Only 24-bit values are supported */
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if (val > 0xFFFFFF)
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return -ERANGE;
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Counter can only be set via Preset Register */
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for (i = 0; i < 3; i++)
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outb(val >> (8 * i), base_offset);
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/* Transfer Preset Register to Counter */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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/* Set Preset Register back to original value */
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val = priv->preset[count->id];
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for (i = 0; i < 3; i++)
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outb(val >> (8 * i), base_offset);
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/* Reset Borrow, Carry, Compare, and Sign flags */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
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/* Reset Error flag */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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static const enum counter_function quad8_count_functions_list[] = {
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COUNTER_FUNCTION_PULSE_DIRECTION,
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COUNTER_FUNCTION_QUADRATURE_X1_A,
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COUNTER_FUNCTION_QUADRATURE_X2_A,
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COUNTER_FUNCTION_QUADRATURE_X4,
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};
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static int quad8_function_read(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function *function)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int id = count->id;
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unsigned long irqflags;
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spin_lock_irqsave(&priv->lock, irqflags);
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if (priv->quadrature_mode[id])
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switch (priv->quadrature_scale[id]) {
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case 0:
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*function = COUNTER_FUNCTION_QUADRATURE_X1_A;
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break;
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case 1:
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*function = COUNTER_FUNCTION_QUADRATURE_X2_A;
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break;
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case 2:
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*function = COUNTER_FUNCTION_QUADRATURE_X4;
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break;
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}
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else
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*function = COUNTER_FUNCTION_PULSE_DIRECTION;
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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static int quad8_function_write(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function function)
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{
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struct quad8 *const priv = counter_priv(counter);
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const int id = count->id;
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unsigned int *const quadrature_mode = priv->quadrature_mode + id;
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unsigned int *const scale = priv->quadrature_scale + id;
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unsigned int *const synchronous_mode = priv->synchronous_mode + id;
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const int base_offset = priv->base + 2 * id + 1;
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unsigned long irqflags;
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unsigned int mode_cfg;
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unsigned int idr_cfg;
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spin_lock_irqsave(&priv->lock, irqflags);
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mode_cfg = priv->count_mode[id] << 1;
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idr_cfg = priv->index_polarity[id] << 1;
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if (function == COUNTER_FUNCTION_PULSE_DIRECTION) {
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*quadrature_mode = 0;
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/* Quadrature scaling only available in quadrature mode */
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*scale = 0;
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/* Synchronous function not supported in non-quadrature mode */
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if (*synchronous_mode) {
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*synchronous_mode = 0;
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/* Disable synchronous function mode */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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}
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} else {
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*quadrature_mode = 1;
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switch (function) {
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case COUNTER_FUNCTION_QUADRATURE_X1_A:
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*scale = 0;
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mode_cfg |= QUAD8_CMR_QUADRATURE_X1;
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break;
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case COUNTER_FUNCTION_QUADRATURE_X2_A:
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*scale = 1;
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mode_cfg |= QUAD8_CMR_QUADRATURE_X2;
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break;
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case COUNTER_FUNCTION_QUADRATURE_X4:
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*scale = 2;
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mode_cfg |= QUAD8_CMR_QUADRATURE_X4;
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break;
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default:
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/* should never reach this path */
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return -EINVAL;
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}
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}
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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static int quad8_direction_read(struct counter_device *counter,
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struct counter_count *count,
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enum counter_count_direction *direction)
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{
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const struct quad8 *const priv = counter_priv(counter);
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unsigned int ud_flag;
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const unsigned int flag_addr = priv->base + 2 * count->id + 1;
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/* U/D flag: nonzero = up, zero = down */
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ud_flag = inb(flag_addr) & QUAD8_FLAG_UD;
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*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
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COUNTER_COUNT_DIRECTION_BACKWARD;
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return 0;
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}
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static const enum counter_synapse_action quad8_index_actions_list[] = {
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COUNTER_SYNAPSE_ACTION_NONE,
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COUNTER_SYNAPSE_ACTION_RISING_EDGE,
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};
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static const enum counter_synapse_action quad8_synapse_actions_list[] = {
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COUNTER_SYNAPSE_ACTION_NONE,
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COUNTER_SYNAPSE_ACTION_RISING_EDGE,
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COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
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COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
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};
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static int quad8_action_read(struct counter_device *counter,
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struct counter_count *count,
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struct counter_synapse *synapse,
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enum counter_synapse_action *action)
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{
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struct quad8 *const priv = counter_priv(counter);
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int err;
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enum counter_function function;
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const size_t signal_a_id = count->synapses[0].signal->id;
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enum counter_count_direction direction;
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/* Handle Index signals */
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if (synapse->signal->id >= 16) {
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if (priv->preset_enable[count->id])
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*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
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else
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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return 0;
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}
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err = quad8_function_read(counter, count, &function);
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if (err)
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return err;
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/* Default action mode */
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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/* Determine action mode based on current count function mode */
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switch (function) {
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case COUNTER_FUNCTION_PULSE_DIRECTION:
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if (synapse->signal->id == signal_a_id)
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*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X1_A:
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if (synapse->signal->id == signal_a_id) {
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err = quad8_direction_read(counter, count, &direction);
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if (err)
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return err;
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if (direction == COUNTER_COUNT_DIRECTION_FORWARD)
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*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
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else
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*action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
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}
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X2_A:
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if (synapse->signal->id == signal_a_id)
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X4:
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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return 0;
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default:
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/* should never reach this path */
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return -EINVAL;
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}
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}
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enum {
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QUAD8_EVENT_CARRY = 0,
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QUAD8_EVENT_COMPARE = 1,
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QUAD8_EVENT_CARRY_BORROW = 2,
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QUAD8_EVENT_INDEX = 3,
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};
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static int quad8_events_configure(struct counter_device *counter)
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{
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struct quad8 *const priv = counter_priv(counter);
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unsigned long irq_enabled = 0;
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unsigned long irqflags;
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struct counter_event_node *event_node;
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unsigned int next_irq_trigger;
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unsigned long ior_cfg;
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unsigned long base_offset;
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spin_lock_irqsave(&priv->lock, irqflags);
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list_for_each_entry(event_node, &counter->events_list, l) {
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switch (event_node->event) {
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case COUNTER_EVENT_OVERFLOW:
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next_irq_trigger = QUAD8_EVENT_CARRY;
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break;
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case COUNTER_EVENT_THRESHOLD:
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next_irq_trigger = QUAD8_EVENT_COMPARE;
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break;
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case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
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next_irq_trigger = QUAD8_EVENT_CARRY_BORROW;
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break;
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case COUNTER_EVENT_INDEX:
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next_irq_trigger = QUAD8_EVENT_INDEX;
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break;
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default:
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/* should never reach this path */
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return -EINVAL;
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}
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/* Skip configuration if it is the same as previously set */
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if (priv->irq_trigger[event_node->channel] == next_irq_trigger)
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continue;
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/* Save new IRQ function configuration */
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priv->irq_trigger[event_node->channel] = next_irq_trigger;
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/* Load configuration to I/O Control Register */
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ior_cfg = priv->ab_enable[event_node->channel] |
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priv->preset_enable[event_node->channel] << 1 |
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priv->irq_trigger[event_node->channel] << 3;
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base_offset = priv->base + 2 * event_node->channel + 1;
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
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/* Enable IRQ line */
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irq_enabled |= BIT(event_node->channel);
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}
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outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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static int quad8_watch_validate(struct counter_device *counter,
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const struct counter_watch *watch)
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{
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struct counter_event_node *event_node;
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if (watch->channel > QUAD8_NUM_COUNTERS - 1)
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return -EINVAL;
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switch (watch->event) {
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case COUNTER_EVENT_OVERFLOW:
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case COUNTER_EVENT_THRESHOLD:
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case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
|
|
case COUNTER_EVENT_INDEX:
|
|
list_for_each_entry(event_node, &counter->next_events_list, l)
|
|
if (watch->channel == event_node->channel &&
|
|
watch->event != event_node->event)
|
|
return -EINVAL;
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static const struct counter_ops quad8_ops = {
|
|
.signal_read = quad8_signal_read,
|
|
.count_read = quad8_count_read,
|
|
.count_write = quad8_count_write,
|
|
.function_read = quad8_function_read,
|
|
.function_write = quad8_function_write,
|
|
.action_read = quad8_action_read,
|
|
.events_configure = quad8_events_configure,
|
|
.watch_validate = quad8_watch_validate,
|
|
};
|
|
|
|
static const char *const quad8_index_polarity_modes[] = {
|
|
"negative",
|
|
"positive"
|
|
};
|
|
|
|
static int quad8_index_polarity_get(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u32 *index_polarity)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id - 16;
|
|
|
|
*index_polarity = priv->index_polarity[channel_id];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_index_polarity_set(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u32 index_polarity)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id - 16;
|
|
const int base_offset = priv->base + 2 * channel_id + 1;
|
|
unsigned long irqflags;
|
|
unsigned int idr_cfg = index_polarity << 1;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
idr_cfg |= priv->synchronous_mode[channel_id];
|
|
|
|
priv->index_polarity[channel_id] = index_polarity;
|
|
|
|
/* Load Index Control configuration to Index Control Register */
|
|
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const char *const quad8_synchronous_modes[] = {
|
|
"non-synchronous",
|
|
"synchronous"
|
|
};
|
|
|
|
static int quad8_synchronous_mode_get(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u32 *synchronous_mode)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id - 16;
|
|
|
|
*synchronous_mode = priv->synchronous_mode[channel_id];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_synchronous_mode_set(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u32 synchronous_mode)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id - 16;
|
|
const int base_offset = priv->base + 2 * channel_id + 1;
|
|
unsigned long irqflags;
|
|
unsigned int idr_cfg = synchronous_mode;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
idr_cfg |= priv->index_polarity[channel_id] << 1;
|
|
|
|
/* Index function must be non-synchronous in non-quadrature mode */
|
|
if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->synchronous_mode[channel_id] = synchronous_mode;
|
|
|
|
/* Load Index Control configuration to Index Control Register */
|
|
outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_floor_read(struct counter_device *counter,
|
|
struct counter_count *count, u64 *floor)
|
|
{
|
|
/* Only a floor of 0 is supported */
|
|
*floor = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_mode_read(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
enum counter_count_mode *cnt_mode)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
|
|
/* Map 104-QUAD-8 count mode to Generic Counter count mode */
|
|
switch (priv->count_mode[count->id]) {
|
|
case 0:
|
|
*cnt_mode = COUNTER_COUNT_MODE_NORMAL;
|
|
break;
|
|
case 1:
|
|
*cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
|
|
break;
|
|
case 2:
|
|
*cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
|
|
break;
|
|
case 3:
|
|
*cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_mode_write(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
enum counter_count_mode cnt_mode)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
unsigned int count_mode;
|
|
unsigned int mode_cfg;
|
|
const int base_offset = priv->base + 2 * count->id + 1;
|
|
unsigned long irqflags;
|
|
|
|
/* Map Generic Counter count mode to 104-QUAD-8 count mode */
|
|
switch (cnt_mode) {
|
|
case COUNTER_COUNT_MODE_NORMAL:
|
|
count_mode = 0;
|
|
break;
|
|
case COUNTER_COUNT_MODE_RANGE_LIMIT:
|
|
count_mode = 1;
|
|
break;
|
|
case COUNTER_COUNT_MODE_NON_RECYCLE:
|
|
count_mode = 2;
|
|
break;
|
|
case COUNTER_COUNT_MODE_MODULO_N:
|
|
count_mode = 3;
|
|
break;
|
|
default:
|
|
/* should never reach this path */
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
priv->count_mode[count->id] = count_mode;
|
|
|
|
/* Set count mode configuration value */
|
|
mode_cfg = count_mode << 1;
|
|
|
|
/* Add quadrature mode configuration */
|
|
if (priv->quadrature_mode[count->id])
|
|
mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
|
|
|
|
/* Load mode configuration to Counter Mode Register */
|
|
outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_enable_read(struct counter_device *counter,
|
|
struct counter_count *count, u8 *enable)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
|
|
*enable = priv->ab_enable[count->id];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_enable_write(struct counter_device *counter,
|
|
struct counter_count *count, u8 enable)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const int base_offset = priv->base + 2 * count->id;
|
|
unsigned long irqflags;
|
|
unsigned int ior_cfg;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
priv->ab_enable[count->id] = enable;
|
|
|
|
ior_cfg = enable | priv->preset_enable[count->id] << 1 |
|
|
priv->irq_trigger[count->id] << 3;
|
|
|
|
/* Load I/O control configuration */
|
|
outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const char *const quad8_noise_error_states[] = {
|
|
"No excessive noise is present at the count inputs",
|
|
"Excessive noise is present at the count inputs"
|
|
};
|
|
|
|
static int quad8_error_noise_get(struct counter_device *counter,
|
|
struct counter_count *count, u32 *noise_error)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
const int base_offset = priv->base + 2 * count->id + 1;
|
|
|
|
*noise_error = !!(inb(base_offset) & QUAD8_FLAG_E);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_preset_read(struct counter_device *counter,
|
|
struct counter_count *count, u64 *preset)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
|
|
*preset = priv->preset[count->id];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void quad8_preset_register_set(struct quad8 *const priv, const int id,
|
|
const unsigned int preset)
|
|
{
|
|
const unsigned int base_offset = priv->base + 2 * id;
|
|
int i;
|
|
|
|
priv->preset[id] = preset;
|
|
|
|
/* Reset Byte Pointer */
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
|
|
|
/* Set Preset Register */
|
|
for (i = 0; i < 3; i++)
|
|
outb(preset >> (8 * i), base_offset);
|
|
}
|
|
|
|
static int quad8_count_preset_write(struct counter_device *counter,
|
|
struct counter_count *count, u64 preset)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
unsigned long irqflags;
|
|
|
|
/* Only 24-bit values are supported */
|
|
if (preset > 0xFFFFFF)
|
|
return -ERANGE;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
quad8_preset_register_set(priv, count->id, preset);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_ceiling_read(struct counter_device *counter,
|
|
struct counter_count *count, u64 *ceiling)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
unsigned long irqflags;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
/* Range Limit and Modulo-N count modes use preset value as ceiling */
|
|
switch (priv->count_mode[count->id]) {
|
|
case 1:
|
|
case 3:
|
|
*ceiling = priv->preset[count->id];
|
|
break;
|
|
default:
|
|
/* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
|
|
*ceiling = 0x1FFFFFF;
|
|
break;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_ceiling_write(struct counter_device *counter,
|
|
struct counter_count *count, u64 ceiling)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
unsigned long irqflags;
|
|
|
|
/* Only 24-bit values are supported */
|
|
if (ceiling > 0xFFFFFF)
|
|
return -ERANGE;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
/* Range Limit and Modulo-N count modes use preset value as ceiling */
|
|
switch (priv->count_mode[count->id]) {
|
|
case 1:
|
|
case 3:
|
|
quad8_preset_register_set(priv, count->id, ceiling);
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
return 0;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int quad8_count_preset_enable_read(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
u8 *preset_enable)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
|
|
*preset_enable = !priv->preset_enable[count->id];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_count_preset_enable_write(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
u8 preset_enable)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const int base_offset = priv->base + 2 * count->id + 1;
|
|
unsigned long irqflags;
|
|
unsigned int ior_cfg;
|
|
|
|
/* Preset enable is active low in Input/Output Control register */
|
|
preset_enable = !preset_enable;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
priv->preset_enable[count->id] = preset_enable;
|
|
|
|
ior_cfg = priv->ab_enable[count->id] | preset_enable << 1 |
|
|
priv->irq_trigger[count->id] << 3;
|
|
|
|
/* Load I/O control configuration to Input / Output Control Register */
|
|
outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_signal_cable_fault_read(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u8 *cable_fault)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id / 2;
|
|
unsigned long irqflags;
|
|
bool disabled;
|
|
unsigned int status;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
disabled = !(priv->cable_fault_enable & BIT(channel_id));
|
|
|
|
if (disabled) {
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Logic 0 = cable fault */
|
|
status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
/* Mask respective channel and invert logic */
|
|
*cable_fault = !(status & BIT(channel_id));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_signal_cable_fault_enable_read(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u8 *enable)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id / 2;
|
|
|
|
*enable = !!(priv->cable_fault_enable & BIT(channel_id));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u8 enable)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id / 2;
|
|
unsigned long irqflags;
|
|
unsigned int cable_fault_enable;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
if (enable)
|
|
priv->cable_fault_enable |= BIT(channel_id);
|
|
else
|
|
priv->cable_fault_enable &= ~BIT(channel_id);
|
|
|
|
/* Enable is active low in Differential Encoder Cable Status register */
|
|
cable_fault_enable = ~priv->cable_fault_enable;
|
|
|
|
outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_signal_fck_prescaler_read(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u8 *prescaler)
|
|
{
|
|
const struct quad8 *const priv = counter_priv(counter);
|
|
|
|
*prescaler = priv->fck_prescaler[signal->id / 2];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
|
|
struct counter_signal *signal,
|
|
u8 prescaler)
|
|
{
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const size_t channel_id = signal->id / 2;
|
|
const int base_offset = priv->base + 2 * channel_id;
|
|
unsigned long irqflags;
|
|
|
|
spin_lock_irqsave(&priv->lock, irqflags);
|
|
|
|
priv->fck_prescaler[channel_id] = prescaler;
|
|
|
|
/* Reset Byte Pointer */
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
|
|
|
/* Set filter clock factor */
|
|
outb(prescaler, base_offset);
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
|
|
base_offset + 1);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct counter_comp quad8_signal_ext[] = {
|
|
COUNTER_COMP_SIGNAL_BOOL("cable_fault", quad8_signal_cable_fault_read,
|
|
NULL),
|
|
COUNTER_COMP_SIGNAL_BOOL("cable_fault_enable",
|
|
quad8_signal_cable_fault_enable_read,
|
|
quad8_signal_cable_fault_enable_write),
|
|
COUNTER_COMP_SIGNAL_U8("filter_clock_prescaler",
|
|
quad8_signal_fck_prescaler_read,
|
|
quad8_signal_fck_prescaler_write)
|
|
};
|
|
|
|
static DEFINE_COUNTER_ENUM(quad8_index_pol_enum, quad8_index_polarity_modes);
|
|
static DEFINE_COUNTER_ENUM(quad8_synch_mode_enum, quad8_synchronous_modes);
|
|
|
|
static struct counter_comp quad8_index_ext[] = {
|
|
COUNTER_COMP_SIGNAL_ENUM("index_polarity", quad8_index_polarity_get,
|
|
quad8_index_polarity_set,
|
|
quad8_index_pol_enum),
|
|
COUNTER_COMP_SIGNAL_ENUM("synchronous_mode", quad8_synchronous_mode_get,
|
|
quad8_synchronous_mode_set,
|
|
quad8_synch_mode_enum),
|
|
};
|
|
|
|
#define QUAD8_QUAD_SIGNAL(_id, _name) { \
|
|
.id = (_id), \
|
|
.name = (_name), \
|
|
.ext = quad8_signal_ext, \
|
|
.num_ext = ARRAY_SIZE(quad8_signal_ext) \
|
|
}
|
|
|
|
#define QUAD8_INDEX_SIGNAL(_id, _name) { \
|
|
.id = (_id), \
|
|
.name = (_name), \
|
|
.ext = quad8_index_ext, \
|
|
.num_ext = ARRAY_SIZE(quad8_index_ext) \
|
|
}
|
|
|
|
static struct counter_signal quad8_signals[] = {
|
|
QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"),
|
|
QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"),
|
|
QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"),
|
|
QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"),
|
|
QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"),
|
|
QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"),
|
|
QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"),
|
|
QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"),
|
|
QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"),
|
|
QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"),
|
|
QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"),
|
|
QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"),
|
|
QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"),
|
|
QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"),
|
|
QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"),
|
|
QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"),
|
|
QUAD8_INDEX_SIGNAL(23, "Channel 8 Index")
|
|
};
|
|
|
|
#define QUAD8_COUNT_SYNAPSES(_id) { \
|
|
{ \
|
|
.actions_list = quad8_synapse_actions_list, \
|
|
.num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
|
|
.signal = quad8_signals + 2 * (_id) \
|
|
}, \
|
|
{ \
|
|
.actions_list = quad8_synapse_actions_list, \
|
|
.num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
|
|
.signal = quad8_signals + 2 * (_id) + 1 \
|
|
}, \
|
|
{ \
|
|
.actions_list = quad8_index_actions_list, \
|
|
.num_actions = ARRAY_SIZE(quad8_index_actions_list), \
|
|
.signal = quad8_signals + 2 * (_id) + 16 \
|
|
} \
|
|
}
|
|
|
|
static struct counter_synapse quad8_count_synapses[][3] = {
|
|
QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1),
|
|
QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3),
|
|
QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5),
|
|
QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7)
|
|
};
|
|
|
|
static const enum counter_count_mode quad8_cnt_modes[] = {
|
|
COUNTER_COUNT_MODE_NORMAL,
|
|
COUNTER_COUNT_MODE_RANGE_LIMIT,
|
|
COUNTER_COUNT_MODE_NON_RECYCLE,
|
|
COUNTER_COUNT_MODE_MODULO_N,
|
|
};
|
|
|
|
static DEFINE_COUNTER_AVAILABLE(quad8_count_mode_available, quad8_cnt_modes);
|
|
|
|
static DEFINE_COUNTER_ENUM(quad8_error_noise_enum, quad8_noise_error_states);
|
|
|
|
static struct counter_comp quad8_count_ext[] = {
|
|
COUNTER_COMP_CEILING(quad8_count_ceiling_read,
|
|
quad8_count_ceiling_write),
|
|
COUNTER_COMP_FLOOR(quad8_count_floor_read, NULL),
|
|
COUNTER_COMP_COUNT_MODE(quad8_count_mode_read, quad8_count_mode_write,
|
|
quad8_count_mode_available),
|
|
COUNTER_COMP_DIRECTION(quad8_direction_read),
|
|
COUNTER_COMP_ENABLE(quad8_count_enable_read, quad8_count_enable_write),
|
|
COUNTER_COMP_COUNT_ENUM("error_noise", quad8_error_noise_get, NULL,
|
|
quad8_error_noise_enum),
|
|
COUNTER_COMP_PRESET(quad8_count_preset_read, quad8_count_preset_write),
|
|
COUNTER_COMP_PRESET_ENABLE(quad8_count_preset_enable_read,
|
|
quad8_count_preset_enable_write),
|
|
};
|
|
|
|
#define QUAD8_COUNT(_id, _cntname) { \
|
|
.id = (_id), \
|
|
.name = (_cntname), \
|
|
.functions_list = quad8_count_functions_list, \
|
|
.num_functions = ARRAY_SIZE(quad8_count_functions_list), \
|
|
.synapses = quad8_count_synapses[(_id)], \
|
|
.num_synapses = 2, \
|
|
.ext = quad8_count_ext, \
|
|
.num_ext = ARRAY_SIZE(quad8_count_ext) \
|
|
}
|
|
|
|
static struct counter_count quad8_counts[] = {
|
|
QUAD8_COUNT(0, "Channel 1 Count"),
|
|
QUAD8_COUNT(1, "Channel 2 Count"),
|
|
QUAD8_COUNT(2, "Channel 3 Count"),
|
|
QUAD8_COUNT(3, "Channel 4 Count"),
|
|
QUAD8_COUNT(4, "Channel 5 Count"),
|
|
QUAD8_COUNT(5, "Channel 6 Count"),
|
|
QUAD8_COUNT(6, "Channel 7 Count"),
|
|
QUAD8_COUNT(7, "Channel 8 Count")
|
|
};
|
|
|
|
static irqreturn_t quad8_irq_handler(int irq, void *private)
|
|
{
|
|
struct counter_device *counter = private;
|
|
struct quad8 *const priv = counter_priv(counter);
|
|
const unsigned long base = priv->base;
|
|
unsigned long irq_status;
|
|
unsigned long channel;
|
|
u8 event;
|
|
|
|
irq_status = inb(base + QUAD8_REG_INTERRUPT_STATUS);
|
|
if (!irq_status)
|
|
return IRQ_NONE;
|
|
|
|
for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) {
|
|
switch (priv->irq_trigger[channel]) {
|
|
case QUAD8_EVENT_CARRY:
|
|
event = COUNTER_EVENT_OVERFLOW;
|
|
break;
|
|
case QUAD8_EVENT_COMPARE:
|
|
event = COUNTER_EVENT_THRESHOLD;
|
|
break;
|
|
case QUAD8_EVENT_CARRY_BORROW:
|
|
event = COUNTER_EVENT_OVERFLOW_UNDERFLOW;
|
|
break;
|
|
case QUAD8_EVENT_INDEX:
|
|
event = COUNTER_EVENT_INDEX;
|
|
break;
|
|
default:
|
|
/* should never reach this path */
|
|
WARN_ONCE(true, "invalid interrupt trigger function %u configured for channel %lu\n",
|
|
priv->irq_trigger[channel], channel);
|
|
continue;
|
|
}
|
|
|
|
counter_push_event(counter, event, channel);
|
|
}
|
|
|
|
/* Clear pending interrupts on device */
|
|
outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int quad8_probe(struct device *dev, unsigned int id)
|
|
{
|
|
struct counter_device *counter;
|
|
struct quad8 *priv;
|
|
int i, j;
|
|
unsigned int base_offset;
|
|
int err;
|
|
|
|
if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
|
|
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
|
|
base[id], base[id] + QUAD8_EXTENT);
|
|
return -EBUSY;
|
|
}
|
|
|
|
counter = devm_counter_alloc(dev, sizeof(*priv));
|
|
if (!counter)
|
|
return -ENOMEM;
|
|
priv = counter_priv(counter);
|
|
|
|
/* Initialize Counter device and driver data */
|
|
counter->name = dev_name(dev);
|
|
counter->parent = dev;
|
|
counter->ops = &quad8_ops;
|
|
counter->counts = quad8_counts;
|
|
counter->num_counts = ARRAY_SIZE(quad8_counts);
|
|
counter->signals = quad8_signals;
|
|
counter->num_signals = ARRAY_SIZE(quad8_signals);
|
|
priv->base = base[id];
|
|
|
|
spin_lock_init(&priv->lock);
|
|
|
|
/* Reset Index/Interrupt Register */
|
|
outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT);
|
|
/* Reset all counters and disable interrupt function */
|
|
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
|
|
/* Set initial configuration for all counters */
|
|
for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
|
|
base_offset = base[id] + 2 * i;
|
|
/* Reset Byte Pointer */
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
|
/* Reset filter clock factor */
|
|
outb(0, base_offset);
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
|
|
base_offset + 1);
|
|
/* Reset Byte Pointer */
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
|
|
/* Reset Preset Register */
|
|
for (j = 0; j < 3; j++)
|
|
outb(0x00, base_offset);
|
|
/* Reset Borrow, Carry, Compare, and Sign flags */
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
|
|
/* Reset Error flag */
|
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
|
|
/* Binary encoding; Normal count; non-quadrature mode */
|
|
outb(QUAD8_CTR_CMR, base_offset + 1);
|
|
/* Disable A and B inputs; preset on index; FLG1 as Carry */
|
|
outb(QUAD8_CTR_IOR, base_offset + 1);
|
|
/* Disable index function; negative index polarity */
|
|
outb(QUAD8_CTR_IDR, base_offset + 1);
|
|
}
|
|
/* Disable Differential Encoder Cable Status for all channels */
|
|
outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS);
|
|
/* Enable all counters and enable interrupt function */
|
|
outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP);
|
|
|
|
err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
|
|
IRQF_SHARED, counter->name, counter);
|
|
if (err)
|
|
return err;
|
|
|
|
err = devm_counter_add(dev, counter);
|
|
if (err < 0)
|
|
return dev_err_probe(dev, err, "Failed to add counter\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct isa_driver quad8_driver = {
|
|
.probe = quad8_probe,
|
|
.driver = {
|
|
.name = "104-quad-8"
|
|
}
|
|
};
|
|
|
|
module_isa_driver(quad8_driver, num_quad8);
|
|
|
|
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
|
|
MODULE_DESCRIPTION("ACCES 104-QUAD-8 driver");
|
|
MODULE_LICENSE("GPL v2");
|