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Add devm_clk_hw_register_gate() - devres-managed version of clk_hw_register_gate() Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchip.com
260 lines
5.7 KiB
C
260 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* Gated clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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/**
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* DOC: basic gatable clock which can gate and ungate it's ouput
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - inherits rate from parent. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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static inline u32 clk_gate_readl(struct clk_gate *gate)
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{
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if (gate->flags & CLK_GATE_BIG_ENDIAN)
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return ioread32be(gate->reg);
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return readl(gate->reg);
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}
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static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
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{
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if (gate->flags & CLK_GATE_BIG_ENDIAN)
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iowrite32be(val, gate->reg);
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else
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writel(val, gate->reg);
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}
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/*
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* It works on following logic:
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*
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* For enabling clock, enable = 1
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* set2dis = 1 -> clear bit -> set = 0
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* set2dis = 0 -> set bit -> set = 1
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*
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* For disabling clock, enable = 0
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* set2dis = 1 -> set bit -> set = 1
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* set2dis = 0 -> clear bit -> set = 0
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*
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* So, result is always: enable xor set2dis.
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*/
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static void clk_gate_endisable(struct clk_hw *hw, int enable)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
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unsigned long flags;
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u32 reg;
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set ^= enable;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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else
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__acquire(gate->lock);
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if (gate->flags & CLK_GATE_HIWORD_MASK) {
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reg = BIT(gate->bit_idx + 16);
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if (set)
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reg |= BIT(gate->bit_idx);
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} else {
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reg = clk_gate_readl(gate);
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if (set)
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reg |= BIT(gate->bit_idx);
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else
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reg &= ~BIT(gate->bit_idx);
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}
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clk_gate_writel(gate, reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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else
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__release(gate->lock);
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}
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static int clk_gate_enable(struct clk_hw *hw)
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{
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clk_gate_endisable(hw, 1);
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return 0;
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}
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static void clk_gate_disable(struct clk_hw *hw)
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{
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clk_gate_endisable(hw, 0);
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}
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int clk_gate_is_enabled(struct clk_hw *hw)
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{
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u32 reg;
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struct clk_gate *gate = to_clk_gate(hw);
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reg = clk_gate_readl(gate);
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/* if a set bit disables this clk, flip it before masking */
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if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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reg ^= BIT(gate->bit_idx);
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reg &= BIT(gate->bit_idx);
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return reg ? 1 : 0;
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}
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EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
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const struct clk_ops clk_gate_ops = {
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.enable = clk_gate_enable,
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.disable = clk_gate_disable,
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.is_enabled = clk_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(clk_gate_ops);
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struct clk_hw *__clk_hw_register_gate(struct device *dev,
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struct device_node *np, const char *name,
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const char *parent_name, const struct clk_hw *parent_hw,
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const struct clk_parent_data *parent_data,
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unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct clk_gate *gate;
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struct clk_hw *hw;
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struct clk_init_data init = {};
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int ret = -EINVAL;
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if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
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if (bit_idx > 15) {
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pr_err("gate bit exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the gate */
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_gate_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.parent_hws = parent_hw ? &parent_hw : NULL;
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init.parent_data = parent_data;
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if (parent_name || parent_hw || parent_data)
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init.num_parents = 1;
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else
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init.num_parents = 0;
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/* struct clk_gate assignments */
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->flags = clk_gate_flags;
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gate->lock = lock;
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gate->hw.init = &init;
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hw = &gate->hw;
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if (dev || !np)
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ret = clk_hw_register(dev, hw);
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else if (np)
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ret = of_clk_hw_register(np, hw);
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if (ret) {
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kfree(gate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(__clk_hw_register_gate);
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struct clk *clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
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bit_idx, clk_gate_flags, lock);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_gate);
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void clk_unregister_gate(struct clk *clk)
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{
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struct clk_gate *gate;
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struct clk_hw *hw;
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hw = __clk_get_hw(clk);
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if (!hw)
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return;
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gate = to_clk_gate(hw);
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clk_unregister(clk);
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kfree(gate);
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}
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EXPORT_SYMBOL_GPL(clk_unregister_gate);
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void clk_hw_unregister_gate(struct clk_hw *hw)
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{
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struct clk_gate *gate;
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gate = to_clk_gate(hw);
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clk_hw_unregister(hw);
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kfree(gate);
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}
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EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);
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static void devm_clk_hw_release_gate(struct device *dev, void *res)
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{
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clk_hw_unregister_gate(*(struct clk_hw **)res);
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}
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struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
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struct device_node *np, const char *name,
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const char *parent_name, const struct clk_hw *parent_hw,
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const struct clk_parent_data *parent_data,
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unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct clk_hw **ptr, *hw;
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ptr = devres_alloc(devm_clk_hw_release_gate, sizeof(*ptr), GFP_KERNEL);
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if (!ptr)
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return ERR_PTR(-ENOMEM);
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hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw,
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parent_data, flags, reg, bit_idx,
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clk_gate_flags, lock);
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if (!IS_ERR(hw)) {
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*ptr = hw;
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devres_add(dev, ptr);
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} else {
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devres_free(ptr);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate);
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