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5edffb9805
Regmap gives us caching, debugging infrastructure and other things for free and does away with open-coded bit-fiddling implementations. Signed-off-by: Daniel Mack <daniel@zonque.org> Link: https://lore.kernel.org/r/20220125093336.226787-10-daniel@zonque.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
638 lines
14 KiB
C
638 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* CS2000 -- CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/of_device.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#define CH_MAX 4
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#define RATIO_REG_SIZE 4
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#define DEVICE_ID 0x1
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#define DEVICE_CTRL 0x2
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#define DEVICE_CFG1 0x3
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#define DEVICE_CFG2 0x4
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#define GLOBAL_CFG 0x5
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#define Ratio_Add(x, nth) (6 + (x * 4) + (nth))
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#define Ratio_Val(x, nth) ((x >> (24 - (8 * nth))) & 0xFF)
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#define Val_Ratio(x, nth) ((x & 0xFF) << (24 - (8 * nth)))
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#define FUNC_CFG1 0x16
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#define FUNC_CFG2 0x17
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/* DEVICE_ID */
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#define REVISION_MASK (0x7)
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#define REVISION_B2_B3 (0x4)
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#define REVISION_C1 (0x6)
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/* DEVICE_CTRL */
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#define PLL_UNLOCK (1 << 7)
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#define AUXOUTDIS (1 << 1)
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#define CLKOUTDIS (1 << 0)
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/* DEVICE_CFG1 */
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#define RSEL(x) (((x) & 0x3) << 3)
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#define RSEL_MASK RSEL(0x3)
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#define AUXOUTSRC(x) (((x) & 0x3) << 1)
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#define AUXOUTSRC_MASK AUXOUTSRC(0x3)
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#define ENDEV1 (0x1)
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/* DEVICE_CFG2 */
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#define AUTORMOD (1 << 3)
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#define LOCKCLK(x) (((x) & 0x3) << 1)
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#define LOCKCLK_MASK LOCKCLK(0x3)
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#define FRACNSRC_MASK (1 << 0)
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#define FRACNSRC_STATIC (0 << 0)
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#define FRACNSRC_DYNAMIC (1 << 0)
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/* GLOBAL_CFG */
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#define FREEZE (1 << 7)
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#define ENDEV2 (0x1)
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/* FUNC_CFG1 */
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#define CLKSKIPEN (1 << 7)
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#define REFCLKDIV(x) (((x) & 0x3) << 3)
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#define REFCLKDIV_MASK REFCLKDIV(0x3)
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/* FUNC_CFG2 */
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#define LFRATIO_MASK (1 << 3)
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#define LFRATIO_20_12 (0 << 3)
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#define LFRATIO_12_20 (1 << 3)
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#define CH_SIZE_ERR(ch) ((ch < 0) || (ch >= CH_MAX))
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#define hw_to_priv(_hw) container_of(_hw, struct cs2000_priv, hw)
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#define priv_to_client(priv) (priv->client)
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#define priv_to_dev(priv) (&(priv_to_client(priv)->dev))
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#define CLK_IN 0
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#define REF_CLK 1
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#define CLK_MAX 2
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static bool cs2000_readable_reg(struct device *dev, unsigned int reg)
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{
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return reg > 0;
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}
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static bool cs2000_writeable_reg(struct device *dev, unsigned int reg)
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{
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return reg != DEVICE_ID;
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}
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static bool cs2000_volatile_reg(struct device *dev, unsigned int reg)
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{
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return reg == DEVICE_CTRL;
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}
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static const struct regmap_config cs2000_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = FUNC_CFG2,
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.readable_reg = cs2000_readable_reg,
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.writeable_reg = cs2000_writeable_reg,
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.volatile_reg = cs2000_volatile_reg,
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};
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struct cs2000_priv {
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struct clk_hw hw;
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struct i2c_client *client;
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struct clk *clk_in;
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struct clk *ref_clk;
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struct regmap *regmap;
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bool dynamic_mode;
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bool lf_ratio;
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bool clk_skip;
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/* suspend/resume */
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unsigned long saved_rate;
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unsigned long saved_parent_rate;
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};
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static const struct of_device_id cs2000_of_match[] = {
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{ .compatible = "cirrus,cs2000-cp", },
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{},
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};
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MODULE_DEVICE_TABLE(of, cs2000_of_match);
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static const struct i2c_device_id cs2000_id[] = {
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{ "cs2000-cp", },
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{}
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};
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MODULE_DEVICE_TABLE(i2c, cs2000_id);
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static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable)
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{
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int ret;
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ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, ENDEV1,
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enable ? ENDEV1 : 0);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, ENDEV2,
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enable ? ENDEV2 : 0);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(priv->regmap, FUNC_CFG1, CLKSKIPEN,
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(enable && priv->clk_skip) ? CLKSKIPEN : 0);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv,
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u32 rate_in)
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{
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u32 val;
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if (rate_in >= 32000000 && rate_in < 56000000)
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val = 0x0;
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else if (rate_in >= 16000000 && rate_in < 28000000)
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val = 0x1;
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else if (rate_in >= 8000000 && rate_in < 14000000)
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val = 0x2;
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else
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return -EINVAL;
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return regmap_update_bits(priv->regmap, FUNC_CFG1,
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REFCLKDIV_MASK,
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REFCLKDIV(val));
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}
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static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
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{
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struct device *dev = priv_to_dev(priv);
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unsigned int i, val;
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int ret;
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for (i = 0; i < 256; i++) {
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ret = regmap_read(priv->regmap, DEVICE_CTRL, &val);
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if (ret < 0)
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return ret;
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if (!(val & PLL_UNLOCK))
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return 0;
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udelay(1);
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}
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dev_err(dev, "pll lock failed\n");
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return -ETIMEDOUT;
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}
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static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable)
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{
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/* enable both AUX_OUT, CLK_OUT */
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return regmap_update_bits(priv->regmap, DEVICE_CTRL,
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(AUXOUTDIS | CLKOUTDIS),
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enable ? 0 :
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(AUXOUTDIS | CLKOUTDIS));
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}
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static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out, bool lf_ratio)
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{
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u64 ratio;
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u32 multiplier = lf_ratio ? 12 : 20;
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/*
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* ratio = rate_out / rate_in * 2^multiplier
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*
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* To avoid over flow, rate_out is u64.
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* The result should be u32.
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*/
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ratio = (u64)rate_out << multiplier;
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do_div(ratio, rate_in);
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return ratio;
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}
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static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in, bool lf_ratio)
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{
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u64 rate_out;
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u32 multiplier = lf_ratio ? 12 : 20;
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/*
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* ratio = rate_out / rate_in * 2^multiplier
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*
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* To avoid over flow, rate_out is u64.
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* The result should be u32 or unsigned long.
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*/
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rate_out = (u64)ratio * rate_in;
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return rate_out >> multiplier;
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}
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static int cs2000_ratio_set(struct cs2000_priv *priv,
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int ch, u32 rate_in, u32 rate_out)
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{
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u32 val;
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unsigned int i;
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int ret;
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if (CH_SIZE_ERR(ch))
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return -EINVAL;
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val = cs2000_rate_to_ratio(rate_in, rate_out, priv->lf_ratio);
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for (i = 0; i < RATIO_REG_SIZE; i++) {
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ret = regmap_write(priv->regmap,
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Ratio_Add(ch, i),
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Ratio_Val(val, i));
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch)
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{
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unsigned int tmp, i;
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u32 val;
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int ret;
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val = 0;
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for (i = 0; i < RATIO_REG_SIZE; i++) {
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ret = regmap_read(priv->regmap, Ratio_Add(ch, i), &tmp);
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if (ret < 0)
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return 0;
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val |= Val_Ratio(tmp, i);
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}
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return val;
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}
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static int cs2000_ratio_select(struct cs2000_priv *priv, int ch)
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{
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int ret;
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u8 fracnsrc;
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if (CH_SIZE_ERR(ch))
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return -EINVAL;
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ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, RSEL_MASK, RSEL(ch));
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if (ret < 0)
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return ret;
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fracnsrc = priv->dynamic_mode ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC;
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ret = regmap_update_bits(priv->regmap, DEVICE_CFG2,
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AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK,
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LOCKCLK(ch) | fracnsrc);
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if (ret < 0)
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return ret;
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return 0;
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}
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static unsigned long cs2000_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cs2000_priv *priv = hw_to_priv(hw);
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int ch = 0; /* it uses ch0 only at this point */
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u32 ratio;
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ratio = cs2000_ratio_get(priv, ch);
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return cs2000_ratio_to_rate(ratio, parent_rate, priv->lf_ratio);
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}
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static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct cs2000_priv *priv = hw_to_priv(hw);
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u32 ratio;
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ratio = cs2000_rate_to_ratio(*parent_rate, rate, priv->lf_ratio);
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return cs2000_ratio_to_rate(ratio, *parent_rate, priv->lf_ratio);
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}
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static int cs2000_select_ratio_mode(struct cs2000_priv *priv,
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unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* From the datasheet:
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*
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* | It is recommended that the 12.20 High-Resolution format be
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* | utilized whenever the desired ratio is less than 4096 since
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* | the output frequency accuracy of the PLL is directly proportional
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* | to the accuracy of the timing reference clock and the resolution
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* | of the R_UD.
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*
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* This mode is only available in dynamic mode.
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*/
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priv->lf_ratio = priv->dynamic_mode && ((rate / parent_rate) > 4096);
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return regmap_update_bits(priv->regmap, FUNC_CFG2, LFRATIO_MASK,
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priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20);
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}
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static int __cs2000_set_rate(struct cs2000_priv *priv, int ch,
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unsigned long rate, unsigned long parent_rate)
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{
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int ret;
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ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, FREEZE);
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if (ret < 0)
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return ret;
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ret = cs2000_select_ratio_mode(priv, rate, parent_rate);
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if (ret < 0)
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return ret;
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ret = cs2000_ratio_set(priv, ch, parent_rate, rate);
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if (ret < 0)
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return ret;
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ret = cs2000_ratio_select(priv, ch);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, 0);
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if (ret < 0)
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return ret;
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priv->saved_rate = rate;
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priv->saved_parent_rate = parent_rate;
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return 0;
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}
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static int cs2000_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct cs2000_priv *priv = hw_to_priv(hw);
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int ch = 0; /* it uses ch0 only at this point */
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return __cs2000_set_rate(priv, ch, rate, parent_rate);
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}
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static int cs2000_set_saved_rate(struct cs2000_priv *priv)
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{
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int ch = 0; /* it uses ch0 only at this point */
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return __cs2000_set_rate(priv, ch,
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priv->saved_rate,
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priv->saved_parent_rate);
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}
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static int cs2000_enable(struct clk_hw *hw)
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{
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struct cs2000_priv *priv = hw_to_priv(hw);
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int ret;
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ret = cs2000_enable_dev_config(priv, true);
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if (ret < 0)
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return ret;
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ret = cs2000_clk_out_enable(priv, true);
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if (ret < 0)
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return ret;
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ret = cs2000_wait_pll_lock(priv);
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if (ret < 0)
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return ret;
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return ret;
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}
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static void cs2000_disable(struct clk_hw *hw)
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{
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struct cs2000_priv *priv = hw_to_priv(hw);
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cs2000_enable_dev_config(priv, false);
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cs2000_clk_out_enable(priv, false);
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}
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static u8 cs2000_get_parent(struct clk_hw *hw)
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{
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struct cs2000_priv *priv = hw_to_priv(hw);
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/*
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* In dynamic mode, output rates are derived from CLK_IN.
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* In static mode, CLK_IN is ignored, so we return REF_CLK instead.
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*/
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return priv->dynamic_mode ? CLK_IN : REF_CLK;
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}
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static const struct clk_ops cs2000_ops = {
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.get_parent = cs2000_get_parent,
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.recalc_rate = cs2000_recalc_rate,
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.round_rate = cs2000_round_rate,
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.set_rate = cs2000_set_rate,
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.prepare = cs2000_enable,
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.unprepare = cs2000_disable,
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};
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static int cs2000_clk_get(struct cs2000_priv *priv)
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{
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struct device *dev = priv_to_dev(priv);
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struct clk *clk_in, *ref_clk;
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clk_in = devm_clk_get(dev, "clk_in");
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/* not yet provided */
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if (IS_ERR(clk_in))
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return -EPROBE_DEFER;
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ref_clk = devm_clk_get(dev, "ref_clk");
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/* not yet provided */
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if (IS_ERR(ref_clk))
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return -EPROBE_DEFER;
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priv->clk_in = clk_in;
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priv->ref_clk = ref_clk;
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return 0;
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}
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static int cs2000_clk_register(struct cs2000_priv *priv)
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{
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struct device *dev = priv_to_dev(priv);
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struct device_node *np = dev->of_node;
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struct clk_init_data init;
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const char *name = np->name;
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static const char *parent_names[CLK_MAX];
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u32 aux_out = 0;
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int ref_clk_rate;
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int ch = 0; /* it uses ch0 only at this point */
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int ret;
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of_property_read_string(np, "clock-output-names", &name);
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priv->dynamic_mode = of_property_read_bool(np, "cirrus,dynamic-mode");
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dev_info(dev, "operating in %s mode\n",
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priv->dynamic_mode ? "dynamic" : "static");
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of_property_read_u32(np, "cirrus,aux-output-source", &aux_out);
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ret = regmap_update_bits(priv->regmap, DEVICE_CFG1,
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AUXOUTSRC_MASK, AUXOUTSRC(aux_out));
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if (ret < 0)
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return ret;
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priv->clk_skip = of_property_read_bool(np, "cirrus,clock-skip");
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ref_clk_rate = clk_get_rate(priv->ref_clk);
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ret = cs2000_ref_clk_bound_rate(priv, ref_clk_rate);
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if (ret < 0)
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return ret;
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if (priv->dynamic_mode) {
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/* Default to low-frequency mode to allow for large ratios */
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priv->lf_ratio = true;
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} else {
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/*
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* set default rate as 1/1.
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* otherwise .set_rate which setup ratio
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* is never called if user requests 1/1 rate
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*/
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ret = __cs2000_set_rate(priv, ch, ref_clk_rate, ref_clk_rate);
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if (ret < 0)
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return ret;
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}
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parent_names[CLK_IN] = __clk_get_name(priv->clk_in);
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parent_names[REF_CLK] = __clk_get_name(priv->ref_clk);
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init.name = name;
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init.ops = &cs2000_ops;
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init.flags = CLK_SET_RATE_GATE;
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init.parent_names = parent_names;
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init.num_parents = ARRAY_SIZE(parent_names);
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priv->hw.init = &init;
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ret = clk_hw_register(dev, &priv->hw);
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if (ret)
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return ret;
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ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &priv->hw);
|
|
if (ret < 0) {
|
|
clk_hw_unregister(&priv->hw);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cs2000_version_print(struct cs2000_priv *priv)
|
|
{
|
|
struct device *dev = priv_to_dev(priv);
|
|
const char *revision;
|
|
unsigned int val;
|
|
int ret;
|
|
|
|
ret = regmap_read(priv->regmap, DEVICE_ID, &val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* CS2000 should be 0x0 */
|
|
if (val >> 3)
|
|
return -EIO;
|
|
|
|
switch (val & REVISION_MASK) {
|
|
case REVISION_B2_B3:
|
|
revision = "B2 / B3";
|
|
break;
|
|
case REVISION_C1:
|
|
revision = "C1";
|
|
break;
|
|
default:
|
|
return -EIO;
|
|
}
|
|
|
|
dev_info(dev, "revision - %s\n", revision);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cs2000_remove(struct i2c_client *client)
|
|
{
|
|
struct cs2000_priv *priv = i2c_get_clientdata(client);
|
|
struct device *dev = priv_to_dev(priv);
|
|
struct device_node *np = dev->of_node;
|
|
|
|
of_clk_del_provider(np);
|
|
|
|
clk_hw_unregister(&priv->hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cs2000_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct cs2000_priv *priv;
|
|
struct device *dev = &client->dev;
|
|
int ret;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->client = client;
|
|
i2c_set_clientdata(client, priv);
|
|
|
|
priv->regmap = devm_regmap_init_i2c(client, &cs2000_regmap_config);
|
|
if (IS_ERR(priv->regmap))
|
|
return PTR_ERR(priv->regmap);
|
|
|
|
ret = cs2000_clk_get(priv);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = cs2000_clk_register(priv);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = cs2000_version_print(priv);
|
|
if (ret < 0)
|
|
goto probe_err;
|
|
|
|
return 0;
|
|
|
|
probe_err:
|
|
cs2000_remove(client);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __maybe_unused cs2000_resume(struct device *dev)
|
|
{
|
|
struct cs2000_priv *priv = dev_get_drvdata(dev);
|
|
|
|
return cs2000_set_saved_rate(priv);
|
|
}
|
|
|
|
static const struct dev_pm_ops cs2000_pm_ops = {
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, cs2000_resume)
|
|
};
|
|
|
|
static struct i2c_driver cs2000_driver = {
|
|
.driver = {
|
|
.name = "cs2000-cp",
|
|
.pm = &cs2000_pm_ops,
|
|
.of_match_table = cs2000_of_match,
|
|
},
|
|
.probe = cs2000_probe,
|
|
.remove = cs2000_remove,
|
|
.id_table = cs2000_id,
|
|
};
|
|
|
|
module_i2c_driver(cs2000_driver);
|
|
|
|
MODULE_DESCRIPTION("CS2000-CP driver");
|
|
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
|
|
MODULE_LICENSE("GPL v2");
|