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6ba7ea7630
No major functional change. Noticed while checking the driver code that this could be used. Saves two lines. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-5-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
593 lines
15 KiB
C
593 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AXI clkgen driver
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*
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* Copyright 2012-2013 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*/
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#define AXI_CLKGEN_V2_REG_RESET 0x40
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#define AXI_CLKGEN_V2_REG_CLKSEL 0x44
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#define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
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#define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
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#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
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#define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
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#define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
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#define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
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#define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
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#define MMCM_REG_CLKOUT5_2 0x07
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#define MMCM_REG_CLKOUT0_1 0x08
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#define MMCM_REG_CLKOUT0_2 0x09
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#define MMCM_REG_CLKOUT6_2 0x13
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#define MMCM_REG_CLK_FB1 0x14
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#define MMCM_REG_CLK_FB2 0x15
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#define MMCM_REG_CLK_DIV 0x16
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#define MMCM_REG_LOCK1 0x18
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#define MMCM_REG_LOCK2 0x19
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#define MMCM_REG_LOCK3 0x1a
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#define MMCM_REG_POWER 0x28
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#define MMCM_REG_FILTER1 0x4e
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#define MMCM_REG_FILTER2 0x4f
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#define MMCM_CLKOUT_NOCOUNT BIT(6)
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#define MMCM_CLK_DIV_DIVIDE BIT(11)
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#define MMCM_CLK_DIV_NOCOUNT BIT(12)
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struct axi_clkgen_limits {
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unsigned int fpfd_min;
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unsigned int fpfd_max;
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unsigned int fvco_min;
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unsigned int fvco_max;
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};
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struct axi_clkgen {
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void __iomem *base;
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struct clk_hw clk_hw;
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struct axi_clkgen_limits limits;
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};
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static uint32_t axi_clkgen_lookup_filter(unsigned int m)
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{
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switch (m) {
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case 0:
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return 0x01001990;
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case 1:
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return 0x01001190;
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case 2:
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return 0x01009890;
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case 3:
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return 0x01001890;
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case 4:
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return 0x01008890;
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case 5 ... 8:
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return 0x01009090;
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case 9 ... 11:
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return 0x01000890;
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case 12:
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return 0x08009090;
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case 13 ... 22:
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return 0x01001090;
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case 23 ... 36:
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return 0x01008090;
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case 37 ... 46:
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return 0x08001090;
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default:
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return 0x08008090;
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}
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}
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static const uint32_t axi_clkgen_lock_table[] = {
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0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
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0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
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0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
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0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
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0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
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0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
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0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
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0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
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0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
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};
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static uint32_t axi_clkgen_lookup_lock(unsigned int m)
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{
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if (m < ARRAY_SIZE(axi_clkgen_lock_table))
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return axi_clkgen_lock_table[m];
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return 0x1f1f00fa;
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}
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static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
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.fpfd_min = 10000,
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.fpfd_max = 450000,
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.fvco_min = 800000,
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.fvco_max = 1600000,
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};
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static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
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.fpfd_min = 10000,
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.fpfd_max = 300000,
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.fvco_min = 600000,
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.fvco_max = 1200000,
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};
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static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
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unsigned long fin, unsigned long fout,
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unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
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{
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unsigned long d, d_min, d_max, _d_min, _d_max;
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unsigned long m, m_min, m_max;
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unsigned long f, dout, best_f, fvco;
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unsigned long fract_shift = 0;
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unsigned long fvco_min_fract, fvco_max_fract;
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fin /= 1000;
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fout /= 1000;
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best_f = ULONG_MAX;
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*best_d = 0;
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*best_m = 0;
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*best_dout = 0;
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d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1);
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d_max = min_t(unsigned long, fin / limits->fpfd_min, 80);
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again:
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fvco_min_fract = limits->fvco_min << fract_shift;
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fvco_max_fract = limits->fvco_max << fract_shift;
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m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
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m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
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for (m = m_min; m <= m_max; m++) {
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_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
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_d_max = min(d_max, fin * m / fvco_min_fract);
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for (d = _d_min; d <= _d_max; d++) {
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fvco = fin * m / d;
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dout = DIV_ROUND_CLOSEST(fvco, fout);
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dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
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f = fvco / dout;
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if (abs(f - fout) < abs(best_f - fout)) {
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best_f = f;
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*best_d = d;
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*best_m = m << (3 - fract_shift);
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*best_dout = dout << (3 - fract_shift);
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if (best_f == fout)
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return;
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}
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}
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}
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/* Lets see if we find a better setting in fractional mode */
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if (fract_shift == 0) {
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fract_shift = 3;
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goto again;
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}
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}
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struct axi_clkgen_div_params {
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unsigned int low;
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unsigned int high;
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unsigned int edge;
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unsigned int nocount;
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unsigned int frac_en;
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unsigned int frac;
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unsigned int frac_wf_f;
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unsigned int frac_wf_r;
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unsigned int frac_phase;
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};
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static void axi_clkgen_calc_clk_params(unsigned int divider,
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unsigned int frac_divider, struct axi_clkgen_div_params *params)
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{
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memset(params, 0x0, sizeof(*params));
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if (divider == 1) {
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params->nocount = 1;
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return;
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}
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if (frac_divider == 0) {
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params->high = divider / 2;
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params->edge = divider % 2;
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params->low = divider - params->high;
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} else {
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params->frac_en = 1;
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params->frac = frac_divider;
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params->high = divider / 2;
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params->edge = divider % 2;
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params->low = params->high;
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if (params->edge == 0) {
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params->high--;
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params->frac_wf_r = 1;
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}
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if (params->edge == 0 || frac_divider == 1)
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params->low--;
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if (((params->edge == 0) ^ (frac_divider == 1)) ||
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(divider == 2 && frac_divider == 1))
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params->frac_wf_f = 1;
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params->frac_phase = params->edge * 4 + frac_divider / 2;
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}
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}
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static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val)
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{
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writel(val, axi_clkgen->base + reg);
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}
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static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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*val = readl(axi_clkgen->base + reg);
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}
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static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
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{
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unsigned int timeout = 10000;
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unsigned int val;
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do {
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axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
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} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
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if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
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return -EIO;
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return val & 0xffff;
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}
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static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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unsigned int reg_val;
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int ret;
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
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reg_val |= (reg << 16);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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*val = ret;
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return 0;
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}
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static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val, unsigned int mask)
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{
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unsigned int reg_val = 0;
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int ret;
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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if (mask != 0xffff) {
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axi_clkgen_mmcm_read(axi_clkgen, reg, ®_val);
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reg_val &= ~mask;
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}
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reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
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return 0;
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}
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static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
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bool enable)
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{
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unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
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if (enable)
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val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
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}
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static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
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{
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return container_of(clk_hw, struct axi_clkgen, clk_hw);
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}
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static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
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unsigned int reg1, unsigned int reg2, unsigned int reg3,
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struct axi_clkgen_div_params *params)
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{
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axi_clkgen_mmcm_write(axi_clkgen, reg1,
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(params->high << 6) | params->low, 0xefff);
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axi_clkgen_mmcm_write(axi_clkgen, reg2,
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(params->frac << 12) | (params->frac_en << 11) |
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(params->frac_wf_r << 10) | (params->edge << 7) |
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(params->nocount << 6), 0x7fff);
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if (reg3 != 0) {
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axi_clkgen_mmcm_write(axi_clkgen, reg3,
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(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
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}
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}
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static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
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unsigned int d, m, dout;
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struct axi_clkgen_div_params params;
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uint32_t power = 0;
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uint32_t filter;
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uint32_t lock;
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if (parent_rate == 0 || rate == 0)
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return -EINVAL;
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axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);
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if (d == 0 || dout == 0 || m == 0)
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return -EINVAL;
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if ((dout & 0x7) != 0 || (m & 0x7) != 0)
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power |= 0x9800;
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
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filter = axi_clkgen_lookup_filter(m - 1);
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lock = axi_clkgen_lookup_lock(m - 1);
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axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms);
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axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
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MMCM_REG_CLKOUT5_2, ¶ms);
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axi_clkgen_calc_clk_params(d, 0, ¶ms);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
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(params.edge << 13) | (params.nocount << 12) |
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(params.high << 6) | params.low, 0x3fff);
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axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms);
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axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
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MMCM_REG_CLKOUT6_2, ¶ms);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
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(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
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(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
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return 0;
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}
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static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
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const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
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unsigned int d, m, dout;
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unsigned long long tmp;
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axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout);
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if (d == 0 || dout == 0 || m == 0)
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return -EINVAL;
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tmp = (unsigned long long)*parent_rate * m;
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tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
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return min_t(unsigned long long, tmp, LONG_MAX);
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}
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static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
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unsigned int reg1, unsigned int reg2)
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{
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unsigned int val1, val2;
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unsigned int div;
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axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
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if (val2 & MMCM_CLKOUT_NOCOUNT)
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return 8;
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axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
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div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
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div <<= 3;
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if (val2 & MMCM_CLK_DIV_DIVIDE) {
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if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
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div += 8;
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else
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div += 16;
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div += (val2 >> 12) & 0x7;
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}
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return div;
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}
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static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
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unsigned long parent_rate)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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unsigned int d, m, dout;
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unsigned long long tmp;
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unsigned int val;
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dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
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MMCM_REG_CLKOUT0_2);
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m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
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MMCM_REG_CLK_FB2);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
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if (val & MMCM_CLK_DIV_NOCOUNT)
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d = 1;
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else
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d = (val & 0x3f) + ((val >> 6) & 0x3f);
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if (d == 0 || dout == 0)
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return 0;
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tmp = (unsigned long long)parent_rate * m;
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tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
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|
|
return min_t(unsigned long long, tmp, ULONG_MAX);
|
|
}
|
|
|
|
static int axi_clkgen_enable(struct clk_hw *clk_hw)
|
|
{
|
|
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
|
|
|
|
axi_clkgen_mmcm_enable(axi_clkgen, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void axi_clkgen_disable(struct clk_hw *clk_hw)
|
|
{
|
|
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
|
|
|
|
axi_clkgen_mmcm_enable(axi_clkgen, false);
|
|
}
|
|
|
|
static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
|
|
{
|
|
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
|
|
|
|
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
|
|
{
|
|
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
|
|
unsigned int parent;
|
|
|
|
axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
|
|
|
|
return parent;
|
|
}
|
|
|
|
static const struct clk_ops axi_clkgen_ops = {
|
|
.recalc_rate = axi_clkgen_recalc_rate,
|
|
.round_rate = axi_clkgen_round_rate,
|
|
.set_rate = axi_clkgen_set_rate,
|
|
.enable = axi_clkgen_enable,
|
|
.disable = axi_clkgen_disable,
|
|
.set_parent = axi_clkgen_set_parent,
|
|
.get_parent = axi_clkgen_get_parent,
|
|
};
|
|
|
|
static int axi_clkgen_probe(struct platform_device *pdev)
|
|
{
|
|
const struct axi_clkgen_limits *dflt_limits;
|
|
struct axi_clkgen *axi_clkgen;
|
|
struct clk_init_data init;
|
|
const char *parent_names[2];
|
|
const char *clk_name;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
dflt_limits = device_get_match_data(&pdev->dev);
|
|
if (!dflt_limits)
|
|
return -ENODEV;
|
|
|
|
axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
|
|
if (!axi_clkgen)
|
|
return -ENOMEM;
|
|
|
|
axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(axi_clkgen->base))
|
|
return PTR_ERR(axi_clkgen->base);
|
|
|
|
init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
|
|
if (init.num_parents < 1 || init.num_parents > 2)
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < init.num_parents; i++) {
|
|
parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
|
|
if (!parent_names[i])
|
|
return -EINVAL;
|
|
}
|
|
|
|
memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits));
|
|
|
|
clk_name = pdev->dev.of_node->name;
|
|
of_property_read_string(pdev->dev.of_node, "clock-output-names",
|
|
&clk_name);
|
|
|
|
init.name = clk_name;
|
|
init.ops = &axi_clkgen_ops;
|
|
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
|
|
init.parent_names = parent_names;
|
|
|
|
axi_clkgen_mmcm_enable(axi_clkgen, false);
|
|
|
|
axi_clkgen->clk_hw.init = &init;
|
|
ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
|
|
&axi_clkgen->clk_hw);
|
|
}
|
|
|
|
static int axi_clkgen_remove(struct platform_device *pdev)
|
|
{
|
|
of_clk_del_provider(pdev->dev.of_node);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id axi_clkgen_ids[] = {
|
|
{
|
|
.compatible = "adi,zynqmp-axi-clkgen-2.00.a",
|
|
.data = &axi_clkgen_zynqmp_default_limits,
|
|
},
|
|
{
|
|
.compatible = "adi,axi-clkgen-2.00.a",
|
|
.data = &axi_clkgen_zynq_default_limits,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
|
|
|
|
static struct platform_driver axi_clkgen_driver = {
|
|
.driver = {
|
|
.name = "adi-axi-clkgen",
|
|
.of_match_table = axi_clkgen_ids,
|
|
},
|
|
.probe = axi_clkgen_probe,
|
|
.remove = axi_clkgen_remove,
|
|
};
|
|
module_platform_driver(axi_clkgen_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
|