mirror of
https://github.com/torvalds/linux.git
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9512433987
clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmJDd+gRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVB4A//QWPv7tssTuHvVDOPz2q9rJFbjG6/fsuY d8i30y4uTSCWO2eErVUNKxRmrR5/DFJZ20cqv5aTXbiUk5BrmCiD0hyb8RZIU4jD Kw+1pEvnbBWR6s5TK0spMS9Nz9Uq8DBwoeczHAVQrRZu0I8AkOvWlVH7GncejYOP KJJSiuByXHRLxudrLWTwwkz3xoDTZBeBcqNbBnatgXnPgSzBh0Uz+0q8r9V9Hugw +TwXoTVt+XDrX2ihPzZlfm9xoOTOP6GoP+FYCo8gCfW4N0VjUDr3+D95rJoI2gp/ O9UyAx1+tMLlkVxuHcX1npHDPX6Nrqan68DBV4LQRdhSO3dfVD95AE16GzMrD+2t nuIzT+rst42UUzipCK/8pHLd/YCcPmIsH4C25ZnaF/I59kI/seF3zbekMTY7hS8D q9sTZYj1X32aHGTtN6QK6QJIscGHYfnSG3M8VLOnhmWDKmW+6AWJ2MVZdcCqDgnS AXnx1p7gwd/lHV8P+e1YoiUyh5a3tJ2CFFdQCu0tPwL0xLehHyfjKqtjYZjL2+hl 6pF8KxEy6BiMEZWqXmIUJK6xWFO9VpQ2uPxtV8pCTIAXmOOPenWhH7lkeTtIDRc0 hzJURj9HEcpEDakC4/16yfr+YnEn/vjhhZ8a4Vymsnl2IsI71C17vDmRer875Bp/ KPMBn6I1naQ= =fP8L -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's one large change in the core clk framework here. We change how clk_set_rate_range() works so that the frequency is re-evaulated each time the rate is changed. Previously we wouldn't let clk providers see a rate that was different if it was still within the range, which could be bad for power if the clk could run slower when a range expands. Now the clk provider can decide to do something differently when the constraints change. This broke Nvidia's clk driver so we had to wait for the fix for that to bake a little more in -next. The rate range patch series also introduced a kunit suite for the clk framework that we're going to extend in the next release. It already made it easy to find corner cases in the rate range patches so I'm excited to see it cover more clk code and increase our confidence in core framework patches in the future. I also added a kunit test for the basic clk gate code and that work will continue to cover more basic clk types: muxes, dividers, etc. Beyond the core code we have the usual set of clk driver updates and additions. Qualcomm again dominates the diffstat here with lots more SoCs being supported and i.MX follows afer that with a similar number of SoCs gaining clk drivers. Beyond those large additions there's drivers being modernized to use clk_parent_data so we can move away from global string names for all the clks in an SoC. Finally there's lots of little fixes all over the clk drivers for typos, warnings, and missing clks that aren't critical and get batched up waiting for the next merge window to open. Nothing super big stands out in the driver pile. Full details are below. Core: - Make clk_set_rate_range() re-evaluate the limits each time - Introduce various clk_set_rate_range() tests - Add clk_drop_range() to drop a previously set range New Drivers: - i.MXRT1050 clock driver and bindings - i.MX8DXL clock driver and bindings - i.MX93 clock driver and bindings - NCO blocks on Apple SoCs - Audio clks on StarFive JH7100 RISC-V SoC - Add support for the new Renesas RZ/V2L SoC - Qualcomm SDX65 A7 PLL - Qualcomm SM6350 GPU clks - Qualcomm SM6125, SM6350, QCS2290 display clks - Qualcomm MSM8226 multimedia clks Updates: - Kunit tests for clk-gate implementation - Terminate arrays with sentinels and make that clearer - Cleanup SPDX tags - Fix typos in comments - Mark mux table as const in clk-mux - Make the all_lists array const - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode - Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on Renesas R-Car S4-8 - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt() - Rework for the imx pll14xx - sama7g5: One low priority fix for GCLK of PDMC - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8 - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3 - Add CAN-FD clocks on Renesas R-Car V3U - Qualcomm SC8280XP RPMCC - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML - Convert various Qualcomm drivers to use clk_parent_data - Remove test clocks from various Qualcomm drivers - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs - Better pixel clk frequency support on Qualcomm RCG2 clks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: zynq: Update the parameters to zynq_clk_register_periph_clk clk: zynq: trivial warning fix clk: Drop the rate range on clk_put() clk: test: Test clk_set_rate_range on orphan mux clk: Initialize orphan req_rate dt-bindings: clock: drop useless consumer example dt-bindings: clock: renesas: Make example 'clocks' parsable clk: qcom: gcc-msm8994: Fix gpll4 width dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() clk: visconti: prevent array overflow in visconti_clk_register_gates() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: sifive: Move all stuff into SoCs header files from C files clk: sifive: Add SoCs prefix in each SoCs-dependent data riscv: dts: Change the macro name of prci in each device node dt-bindings: change the macro name of prci in header files and example clk: sifive: duplicate the macro definitions for the time being clk: qcom: sm6125-gcc: fix typos in comments clk: ti: clkctrl: fix typos in comments ...
467 lines
14 KiB
Plaintext
467 lines
14 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config HAVE_CLK
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bool
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help
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The <linux/clk.h> calls support software clock gating and
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thus are a key power management tool on many systems.
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config HAVE_CLK_PREPARE
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bool
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config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
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bool
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select HAVE_CLK
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help
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Select this option when the clock API in <linux/clk.h> is implemented
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by platform/architecture code. This method is deprecated. Modern
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code should select COMMON_CLK instead and not define a custom
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'struct clk'.
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menuconfig COMMON_CLK
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bool "Common Clock Framework"
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depends on !HAVE_LEGACY_CLK
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select HAVE_CLK_PREPARE
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select HAVE_CLK
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select SRCU
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select RATIONAL
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help
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The common clock framework is a single definition of struct
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clk, useful across many platforms, as well as an
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implementation of the clock API in include/linux/clk.h.
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Architectures utilizing the common struct clk should select
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this option.
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if COMMON_CLK
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config COMMON_CLK_WM831X
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tristate "Clock driver for WM831x/2x PMICs"
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depends on MFD_WM831X
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help
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Supports the clocking subsystem of the WM831x/2x series of
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PMICs from Wolfson Microelectronics.
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source "drivers/clk/versatile/Kconfig"
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config CLK_HSDK
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bool "PLL Driver for HSDK platform"
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depends on ARC_SOC_HSDK || COMPILE_TEST
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depends on HAS_IOMEM
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help
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This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
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control.
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config LMK04832
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tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
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depends on SPI
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select REGMAP_SPI
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help
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Say yes here to build support for Texas Instruments' LMK04832 Ultra
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Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
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config COMMON_CLK_APPLE_NCO
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tristate "Clock driver for Apple SoC NCOs"
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depends on ARCH_APPLE || COMPILE_TEST
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default ARCH_APPLE
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help
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This driver supports NCO (Numerically Controlled Oscillator) blocks
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found on Apple SoCs such as t8103 (M1). The blocks are typically
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generators of audio clocks.
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config COMMON_CLK_MAX77686
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tristate "Clock driver for Maxim 77620/77686/77802 MFD"
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depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
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help
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This driver supports Maxim 77620/77686/77802 crystal oscillator
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clock.
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config COMMON_CLK_MAX9485
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tristate "Maxim 9485 Programmable Clock Generator"
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depends on I2C
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help
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This driver supports Maxim 9485 Programmable Audio Clock Generator
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config COMMON_CLK_RK808
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tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
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depends on MFD_RK808
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help
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This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
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These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
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Clkout1 is always on, Clkout2 can off by control register.
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config COMMON_CLK_HI655X
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tristate "Clock driver for Hi655x" if EXPERT
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depends on (MFD_HI655X_PMIC || COMPILE_TEST)
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depends on REGMAP
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default MFD_HI655X_PMIC
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help
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This driver supports the hi655x PMIC clock. This
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multi-function device has one fixed-rate oscillator, clocked
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at 32KHz.
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config COMMON_CLK_SCMI
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tristate "Clock driver controlled via SCMI interface"
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depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
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help
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This driver provides support for clocks that are controlled
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by firmware that implements the SCMI interface.
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This driver uses SCMI Message Protocol to interact with the
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firmware providing all the clock controls.
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config COMMON_CLK_SCPI
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tristate "Clock driver controlled via SCPI interface"
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depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
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help
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This driver provides support for clocks that are controlled
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by firmware that implements the SCPI interface.
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This driver uses SCPI Message Protocol to interact with the
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firmware providing all the clock controls.
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config COMMON_CLK_SI5341
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tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
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depends on I2C
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select REGMAP_I2C
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help
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This driver supports Silicon Labs Si5341 and Si5340 programmable clock
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generators. Not all features of these chips are currently supported
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by the driver, in particular it only supports XTAL input. The chip can
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be pre-programmed to support other configurations and features not yet
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implemented in the driver.
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config COMMON_CLK_SI5351
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tristate "Clock driver for SiLabs 5351A/B/C"
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depends on I2C
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select REGMAP_I2C
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help
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This driver supports Silicon Labs 5351A/B/C programmable clock
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generators.
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config COMMON_CLK_SI514
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tristate "Clock driver for SiLabs 514 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports the Silicon Labs 514 programmable clock
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generator.
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config COMMON_CLK_SI544
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tristate "Clock driver for SiLabs 544 devices"
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depends on I2C
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select REGMAP_I2C
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help
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This driver supports the Silicon Labs 544 programmable clock
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generator.
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config COMMON_CLK_SI570
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tristate "Clock driver for SiLabs 570 and compatible devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports Silicon Labs 570/571/598/599 programmable
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clock generators.
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config COMMON_CLK_BM1880
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bool "Clock driver for Bitmain BM1880 SoC"
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depends on ARCH_BITMAIN || COMPILE_TEST
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default ARCH_BITMAIN
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help
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This driver supports the clocks on Bitmain BM1880 SoC.
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config COMMON_CLK_CDCE706
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tristate "Clock driver for TI CDCE706 clock synthesizer"
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depends on I2C
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select REGMAP_I2C
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help
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This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
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config COMMON_CLK_TPS68470
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tristate "Clock Driver for TI TPS68470 PMIC"
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depends on I2C
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depends on INTEL_SKL_INT3472 || COMPILE_TEST
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select REGMAP_I2C
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help
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This driver supports the clocks provided by the TPS68470 PMIC.
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config COMMON_CLK_CDCE925
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tristate "Clock driver for TI CDCE913/925/937/949 devices"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports the TI CDCE913/925/937/949 programmable clock
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synthesizer. Each chip has different number of PLLs and outputs.
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For example, the CDCE925 contains two PLLs with spread-spectrum
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clocking support and five output dividers. The driver only supports
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the following setup, and uses a fixed setting for the output muxes.
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Y1 is derived from the input clock
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Y2 and Y3 derive from PLL1
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Y4 and Y5 derive from PLL2
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Given a target output frequency, the driver will set the PLL and
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divider to best approximate the desired output.
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config COMMON_CLK_CS2000_CP
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tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
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depends on I2C
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select REGMAP_I2C
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help
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If you say yes here you get support for the CS2000 clock multiplier.
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config COMMON_CLK_FSL_FLEXSPI
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tristate "Clock driver for FlexSPI on Layerscape SoCs"
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depends on ARCH_LAYERSCAPE || COMPILE_TEST
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default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
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help
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On Layerscape SoCs there is a special clock for the FlexSPI
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interface.
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config COMMON_CLK_FSL_SAI
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bool "Clock driver for BCLK of Freescale SAI cores"
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depends on ARCH_LAYERSCAPE || COMPILE_TEST
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help
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This driver supports the Freescale SAI (Synchronous Audio Interface)
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to be used as a generic clock output. Some SoCs have restrictions
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regarding the possible pin multiplexer settings. Eg. on some SoCs
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two SAI interfaces can only be enabled together. If just one is
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needed, the BCLK pin of the second one can be used as general
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purpose clock output. Ideally, it can be used to drive an audio
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codec (sometimes known as MCLK).
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config COMMON_CLK_GEMINI
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bool "Clock driver for Cortina Systems Gemini SoC"
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depends on ARCH_GEMINI || COMPILE_TEST
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select MFD_SYSCON
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select RESET_CONTROLLER
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help
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This driver supports the SoC clocks on the Cortina Systems Gemini
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platform, also known as SL3516 or CS3516.
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config COMMON_CLK_LAN966X
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bool "Generic Clock Controller driver for LAN966X SoC"
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depends on HAS_IOMEM
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depends on OF
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depends on SOC_LAN966 || COMPILE_TEST
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help
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This driver provides support for Generic Clock Controller(GCK) on
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LAN966X SoC. GCK generates and supplies clock to various peripherals
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within the SoC.
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config COMMON_CLK_ASPEED
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bool "Clock driver for Aspeed BMC SoCs"
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depends on ARCH_ASPEED || COMPILE_TEST
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default ARCH_ASPEED
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select MFD_SYSCON
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select RESET_CONTROLLER
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help
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This driver supports the SoC clocks on the Aspeed BMC platforms.
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The G4 and G5 series, including the ast2400 and ast2500, are supported
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by this driver.
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config COMMON_CLK_S2MPS11
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tristate "Clock driver for S2MPS1X/S5M8767 MFD"
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depends on MFD_SEC_CORE || COMPILE_TEST
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help
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This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
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clock. These multi-function devices have two (S2MPS14) or three
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(S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
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config CLK_TWL6040
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tristate "External McPDM functional clock from twl6040"
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depends on TWL6040_CORE
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help
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Enable the external functional clock support on OMAP4+ platforms for
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McPDM. McPDM module is using the external bit clock on the McPDM bus
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as functional clock.
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config COMMON_CLK_AXI_CLKGEN
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tristate "AXI clkgen driver"
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depends on HAS_IOMEM || COMPILE_TEST
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depends on OF
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help
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Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
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FPGAs. It is commonly used in Analog Devices' reference designs.
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config CLK_QORIQ
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bool "Clock driver for Freescale QorIQ platforms"
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depends on OF
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depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
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help
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This adds the clock driver support for Freescale QorIQ platforms
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using common clock framework.
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config CLK_LS1028A_PLLDIG
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tristate "Clock driver for LS1028A Display output"
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depends on ARCH_LAYERSCAPE || COMPILE_TEST
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default ARCH_LAYERSCAPE
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help
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This driver support the Display output interfaces(LCD, DPHY) pixel clocks
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of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
|
|
features of the PLL are currently supported by the driver. By default,
|
|
configured bypass mode with this PLL.
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|
|
|
config COMMON_CLK_XGENE
|
|
bool "Clock driver for APM XGene SoC"
|
|
default ARCH_XGENE
|
|
depends on ARM64 || COMPILE_TEST
|
|
help
|
|
Support for the APM X-Gene SoC reference, PLL, and device clocks.
|
|
|
|
config COMMON_CLK_LOCHNAGAR
|
|
tristate "Cirrus Logic Lochnagar clock driver"
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|
depends on MFD_LOCHNAGAR
|
|
help
|
|
This driver supports the clocking features of the Cirrus Logic
|
|
Lochnagar audio development board.
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|
|
|
config COMMON_CLK_NXP
|
|
def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
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|
select REGMAP_MMIO if ARCH_LPC32XX
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|
select MFD_SYSCON if ARCH_LPC18XX
|
|
help
|
|
Support for clock providers on NXP platforms.
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|
|
|
config COMMON_CLK_PALMAS
|
|
tristate "Clock driver for TI Palmas devices"
|
|
depends on MFD_PALMAS
|
|
help
|
|
This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
|
|
using common clock framework.
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|
|
|
config COMMON_CLK_PWM
|
|
tristate "Clock driver for PWMs used as clock outputs"
|
|
depends on PWM
|
|
help
|
|
Adapter driver so that any PWM output can be (mis)used as clock signal
|
|
at 50% duty cycle.
|
|
|
|
config COMMON_CLK_PXA
|
|
def_bool COMMON_CLK && ARCH_PXA
|
|
help
|
|
Support for the Marvell PXA SoC.
|
|
|
|
config COMMON_CLK_OXNAS
|
|
bool "Clock driver for the OXNAS SoC Family"
|
|
depends on ARCH_OXNAS || COMPILE_TEST
|
|
select MFD_SYSCON
|
|
help
|
|
Support for the OXNAS SoC Family clocks.
|
|
|
|
config COMMON_CLK_RS9_PCIE
|
|
tristate "Clock driver for Renesas 9-series PCIe clock generators"
|
|
depends on I2C
|
|
depends on OF
|
|
select REGMAP_I2C
|
|
help
|
|
This driver supports the Renesas 9-series PCIe clock generator
|
|
models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
|
|
|
|
config COMMON_CLK_VC5
|
|
tristate "Clock driver for IDT VersaClock 5,6 devices"
|
|
depends on I2C
|
|
depends on OF
|
|
select REGMAP_I2C
|
|
help
|
|
This driver supports the IDT VersaClock 5 and VersaClock 6
|
|
programmable clock generators.
|
|
|
|
config COMMON_CLK_STM32MP157
|
|
def_bool COMMON_CLK && MACH_STM32MP157
|
|
help
|
|
Support for stm32mp157 SoC family clocks
|
|
|
|
config COMMON_CLK_STM32F
|
|
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
|
|
help
|
|
Support for stm32f4 and stm32f7 SoC families clocks
|
|
|
|
config COMMON_CLK_STM32H7
|
|
def_bool COMMON_CLK && MACH_STM32H743
|
|
help
|
|
Support for stm32h7 SoC family clocks
|
|
|
|
config COMMON_CLK_MMP2
|
|
def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
|
|
help
|
|
Support for Marvell MMP2 and MMP3 SoC clocks
|
|
|
|
config COMMON_CLK_MMP2_AUDIO
|
|
tristate "Clock driver for MMP2 Audio subsystem"
|
|
depends on COMMON_CLK_MMP2 || COMPILE_TEST
|
|
help
|
|
This driver supports clocks for Audio subsystem on MMP2 SoC.
|
|
|
|
config COMMON_CLK_BD718XX
|
|
tristate "Clock driver for 32K clk gates on ROHM PMICs"
|
|
depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
|
|
help
|
|
This driver supports ROHM BD71837, BD71847, BD71850, BD71815
|
|
and BD71828 PMICs clock gates.
|
|
|
|
config COMMON_CLK_FIXED_MMIO
|
|
bool "Clock driver for Memory Mapped Fixed values"
|
|
depends on COMMON_CLK && OF
|
|
help
|
|
Support for Memory Mapped IO Fixed clocks
|
|
|
|
config COMMON_CLK_K210
|
|
bool "Clock driver for the Canaan Kendryte K210 SoC"
|
|
depends on OF && RISCV && SOC_CANAAN
|
|
default SOC_CANAAN
|
|
help
|
|
Support for the Canaan Kendryte K210 RISC-V SoC clocks.
|
|
|
|
source "drivers/clk/actions/Kconfig"
|
|
source "drivers/clk/analogbits/Kconfig"
|
|
source "drivers/clk/baikal-t1/Kconfig"
|
|
source "drivers/clk/bcm/Kconfig"
|
|
source "drivers/clk/hisilicon/Kconfig"
|
|
source "drivers/clk/imgtec/Kconfig"
|
|
source "drivers/clk/imx/Kconfig"
|
|
source "drivers/clk/ingenic/Kconfig"
|
|
source "drivers/clk/keystone/Kconfig"
|
|
source "drivers/clk/mediatek/Kconfig"
|
|
source "drivers/clk/meson/Kconfig"
|
|
source "drivers/clk/mstar/Kconfig"
|
|
source "drivers/clk/microchip/Kconfig"
|
|
source "drivers/clk/mvebu/Kconfig"
|
|
source "drivers/clk/pistachio/Kconfig"
|
|
source "drivers/clk/qcom/Kconfig"
|
|
source "drivers/clk/ralink/Kconfig"
|
|
source "drivers/clk/renesas/Kconfig"
|
|
source "drivers/clk/rockchip/Kconfig"
|
|
source "drivers/clk/samsung/Kconfig"
|
|
source "drivers/clk/sifive/Kconfig"
|
|
source "drivers/clk/socfpga/Kconfig"
|
|
source "drivers/clk/sprd/Kconfig"
|
|
source "drivers/clk/starfive/Kconfig"
|
|
source "drivers/clk/sunxi/Kconfig"
|
|
source "drivers/clk/sunxi-ng/Kconfig"
|
|
source "drivers/clk/tegra/Kconfig"
|
|
source "drivers/clk/ti/Kconfig"
|
|
source "drivers/clk/uniphier/Kconfig"
|
|
source "drivers/clk/visconti/Kconfig"
|
|
source "drivers/clk/x86/Kconfig"
|
|
source "drivers/clk/xilinx/Kconfig"
|
|
source "drivers/clk/zynqmp/Kconfig"
|
|
|
|
# Kunit test cases
|
|
config CLK_KUNIT_TEST
|
|
tristate "Basic Clock Framework Kunit Tests" if !KUNIT_ALL_TESTS
|
|
depends on KUNIT
|
|
default KUNIT_ALL_TESTS
|
|
help
|
|
Kunit tests for the common clock framework.
|
|
|
|
config CLK_GATE_KUNIT_TEST
|
|
tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS
|
|
depends on KUNIT
|
|
default KUNIT_ALL_TESTS
|
|
help
|
|
Kunit test for the basic clk gate type.
|
|
|
|
endif
|