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Pull irq domain ARM updates from Thomas Gleixner: "This set of changes make use of hierarchical irqdomains to provide: - MSI/ITS support for GICv3 - MSI support for GICv2m - Interrupt polarity extender for GICv1 Marc has come more cleanups for the existing extension hooks of GIC in the pipeline, but they are going to be 3.20 material" * 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) irqchip: gicv3-its: Fix ITT allocation irqchip: gicv3-its: Move some alloc/free code to activate/deactivate irqchip: gicv3-its: Fix domain free in multi-MSI case irqchip: gic: Remove warning by including linux/irqdomain.h irqchip: gic-v2m: Add DT bindings for GICv2m irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell irqchip: mtk-sysirq: dt-bindings: Add bindings for mediatek sysirq irqchip: mtk-sysirq: Add sysirq interrupt polarity support irqchip: gic: Support hierarchy irq domain. irqchip: GICv3: Binding updates for ITS irqchip: GICv3: ITS: enable compilation of the ITS driver irqchip: GICv3: ITS: plug ITS init into main GICv3 code irqchip: GICv3: ITS: DT probing and initialization irqchip: GICv3: ITS: MSI support irqchip: GICv3: ITS: device allocation and configuration irqchip: GICv3: ITS: tables allocators irqchip: GICv3: ITS: LPI allocator irqchip: GICv3: ITS: irqchip implementation irqchip: GICv3: ITS command queue irqchip: GICv3: rework redistributor structure ...
153 lines
4.7 KiB
Plaintext
153 lines
4.7 KiB
Plaintext
* ARM Generic Interrupt Controller
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ARM SMP cores are often associated with a GIC, providing per processor
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interrupts (PPI), shared processor interrupts (SPI) and software
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generated interrupts (SGI).
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Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
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Secondary GICs are cascaded into the upward interrupt controller and do not
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have PPIs or SGIs.
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Main node required properties:
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- compatible : should be one of:
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"arm,gic-400"
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"arm,cortex-a15-gic"
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"arm,cortex-a9-gic"
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"arm,cortex-a7-gic"
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"arm,arm11mp-gic"
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"brcm,brahma-b15-gic"
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"arm,arm1176jzf-devchip-gic"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 3.
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The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
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interrupts.
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The 2nd cell contains the interrupt number for the interrupt type.
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SPI interrupts are in the range [0-987]. PPI interrupts are in the
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range [0-15].
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The 3rd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = low-to-high edge triggered
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2 = high-to-low edge triggered
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4 = active high level-sensitive
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8 = active low level-sensitive
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bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
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the 8 possible cpus attached to the GIC. A bit set to '1' indicated
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the interrupt is wired to that CPU. Only valid for PPI interrupts.
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- reg : Specifies base physical address(s) and size of the GIC registers. The
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first region is the GIC distributor register base and size. The 2nd region is
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the GIC cpu interface register base and size.
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Optional
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- interrupts : Interrupt source of the parent interrupt controller on
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secondary GICs, or VGIC maintenance interrupt on primary GIC (see
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below).
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- cpu-offset : per-cpu offset within the distributor and cpu interface
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regions, used when the GIC doesn't have banked registers. The offset is
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cpu-offset * cpu-nr.
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- arm,routable-irqs : Total number of gic irq inputs which are not directly
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connected from the peripherals, but are routed dynamically
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by a crossbar/multiplexer preceding the GIC. The GIC irq
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input line is assigned dynamically when the corresponding
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peripheral's crossbar line is mapped.
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Example:
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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arm,routable-irqs = <160>;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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};
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* GIC virtualization extensions (VGIC)
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For ARM cores that support the virtualization extensions, additional
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properties must be described (they only exist if the GIC is the
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primary interrupt controller).
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Required properties:
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- reg : Additional regions specifying the base physical address and
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size of the VGIC registers. The first additional region is the GIC
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virtual interface control register base and size. The 2nd additional
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region is the GIC virtual cpu interface register base and size.
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- interrupts : VGIC maintenance interrupt.
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Example:
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interrupt-controller@2c001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2c001000 0x1000>,
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<0x2c002000 0x1000>,
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<0x2c004000 0x2000>,
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<0x2c006000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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* GICv2m extension for MSI/MSI-x support (Optional)
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Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
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This is enabled by specifying v2m sub-node(s).
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Required properties:
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- compatible : The value here should contain "arm,gic-v2m-frame".
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- msi-controller : Identifies the node as an MSI controller.
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- reg : GICv2m MSI interface register base and size
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Optional properties:
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- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
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value, this property should contain the SPI base of
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the MSI frame, overriding the HW value.
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- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
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value, this property should contain the number of
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SPIs assigned to the frame, overriding the HW value.
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Example:
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interrupt-controller@e1101000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller;
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interrupts = <1 8 0xf04>;
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ranges = <0 0 0 0xe1100000 0 0x100000>;
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reg = <0x0 0xe1110000 0 0x01000>,
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<0x0 0xe112f000 0 0x02000>,
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<0x0 0xe1140000 0 0x10000>,
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<0x0 0xe1160000 0 0x10000>;
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v2m0: v2m@0x8000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x80000 0 0x1000>;
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};
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....
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v2mN: v2m@0x9000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x90000 0 0x1000>;
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};
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};
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