mirror of
https://github.com/torvalds/linux.git
synced 2024-12-19 17:41:29 +00:00
65b5732d24
Some 32-bit (ARMv7) systems are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset (CNTVOFF) between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) On systems like the above, it doesn't make sense to use the virtual counter. There's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. This adds an optional property which can inform the kernel of this situation, and firmware is free to remove the property if it is going to initialize the CNTVOFF registers when each CPU comes out of reset. Currently, the best course of action in this case is to use the physical timer, which is why it is important that CNTHCTL hasn't been changed from its reset value and it's a reasonable assumption given that the firmware has never entered HYP mode. Note that it's been said that on ARMv8 systems the firmware and kernel really can't be architected as described above. That means using the physical timer like this really only makes sense for ARMv7 systems. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Sonny Rao <sonnyrao@chromium.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
93 lines
2.5 KiB
Plaintext
93 lines
2.5 KiB
Plaintext
* ARM architected timer
|
|
|
|
ARM cores may have a per-core architected timer, which provides per-cpu timers,
|
|
or a memory mapped architected timer, which provides up to 8 frames with a
|
|
physical and optional virtual timer per frame.
|
|
|
|
The per-core architected timer is attached to a GIC to deliver its
|
|
per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
|
|
to deliver its interrupts via SPIs.
|
|
|
|
** CP15 Timer node properties:
|
|
|
|
- compatible : Should at least contain one of
|
|
"arm,armv7-timer"
|
|
"arm,armv8-timer"
|
|
|
|
- interrupts : Interrupt list for secure, non-secure, virtual and
|
|
hypervisor timers, in that order.
|
|
|
|
- clock-frequency : The frequency of the main counter, in Hz. Optional.
|
|
|
|
- always-on : a boolean property. If present, the timer is powered through an
|
|
always-on power domain, therefore it never loses context.
|
|
|
|
** Optional properties:
|
|
|
|
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
|
|
any of the generic timer CPU registers, which contain their
|
|
architecturally-defined reset values. Only supported for 32-bit
|
|
systems which follow the ARMv7 architected reset values.
|
|
|
|
|
|
Example:
|
|
|
|
timer {
|
|
compatible = "arm,cortex-a15-timer",
|
|
"arm,armv7-timer";
|
|
interrupts = <1 13 0xf08>,
|
|
<1 14 0xf08>,
|
|
<1 11 0xf08>,
|
|
<1 10 0xf08>;
|
|
clock-frequency = <100000000>;
|
|
};
|
|
|
|
** Memory mapped timer node properties:
|
|
|
|
- compatible : Should at least contain "arm,armv7-timer-mem".
|
|
|
|
- clock-frequency : The frequency of the main counter, in Hz. Optional.
|
|
|
|
- reg : The control frame base address.
|
|
|
|
Note that #address-cells, #size-cells, and ranges shall be present to ensure
|
|
the CPU can address a frame's registers.
|
|
|
|
A timer node has up to 8 frame sub-nodes, each with the following properties:
|
|
|
|
- frame-number: 0 to 7.
|
|
|
|
- interrupts : Interrupt list for physical and virtual timers in that order.
|
|
The virtual timer interrupt is optional.
|
|
|
|
- reg : The first and second view base addresses in that order. The second view
|
|
base address is optional.
|
|
|
|
- status : "disabled" indicates the frame is not available for use. Optional.
|
|
|
|
Example:
|
|
|
|
timer@f0000000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
reg = <0xf0000000 0x1000>;
|
|
clock-frequency = <50000000>;
|
|
|
|
frame@f0001000 {
|
|
frame-number = <0>
|
|
interrupts = <0 13 0x8>,
|
|
<0 14 0x8>;
|
|
reg = <0xf0001000 0x1000>,
|
|
<0xf0002000 0x1000>;
|
|
};
|
|
|
|
frame@f0003000 {
|
|
frame-number = <1>
|
|
interrupts = <0 15 0x8>;
|
|
reg = <0xf0003000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|